Apr 2024 – Present · 2 yrs 2 mos

• Requirements, Architecture, Development, Testing and Maintenance Topics for Communication, Accelerators & Infotainment modules. Also overall System level and Methodology topics for the project.
• MCs: TC3x, TC4x, Next Generation.
• System: Ethernet, Communication Accelerators for Can/Ethernet, Audio Sub System with Media Clock Recovery Topics.
• Methodology:
• Python based Web Dashboards hosted on Cloud,
• Parsing, Data Extraction and Report Generation to derive key project insights,
• Test Methodology Topics for complex systems.
• Prompt Engineering and Copilot.

Apr 2023 – Present · 3 yrs 2 mos

• New IPs-Hsphy, Audio
• Stacks-Lwip (Integration of Lwip to low level drivers)
• Transceivers- RTL8201, RTL8211, RTL8221, DP83825
• Ethernet modes: MII, RMII, RGMII, SGMII, 10Base-T1S
• Maintenance-Rest of COMM IPs
• Advance Topics: Ethernet Virtualization, Can & Ethernet Routing Accelerators

Apr 2021 – Apr 2023 · 2 yrs

• Primary work: Develop iLLD drivers (Bare metal drivers) for Aurix A3G devices (TC49, TC4D, TC43,...)
• 1. Ethernet Advanced Communication Stack and Libraries: S/w Architecture, Driver Development for advanced features of GETH. Basic layers of DMA, MTL, MAC, Bridge, Descriptors, S/w services and comm stack were enhanced. New libraries were developed for MDIO, MMC, VLAN, Filtering, AVB, PPS, PTP, Traffic Classes, Arbitration Management, etc
• 2. GETH driver testing and reference demo applications on silicon for post silicon validation activities.
• 3. Develop/Enhance drivers for CRE 2.0 and DRE 2.0 for TC4D (2nd derivative of Aurix 3rd Gen microcontroller series)
• 4. Requirements, S/w Architecture and Driver Development for LETH (Light Ethernet IP based on Synopsis eQoS) having a bridge and 4 ports.
• 5. Support SOCV for LETH Verification activities.
• 6. Update all legacy comm drivers from TC49.
• Mentoring:
• 1. Coach intern to develop secure encrypted ethernet communication reference demos on virtual prototype platform based on GETH and CSS.
• 2. Coach fresher to perform unit testing for GETH for code coverage requirements.
• 3. PoC and implementation for automated traceability report generation using internal traceability tool called Vesper.
• 4. Coach juniors on comm validation topics/debugging on silicon.
• Reporting:
• 1. Interface to project management and quality.
• Execution:
• 1. Track execution activities of team, support team as required and ensure all release activities are performed in time and within defined process quality.
• Other activities:
• 1. Collaboration across concept teams and different verification teams to achieve Tapeout.
• 2. Support AEs and Technical marketing teams with demos.
• 3. Support iLLD application development for all stakeholders.
• 4. Maintain legacy drivers.

Sep 2020 – Mar 2021 · 6 mos

• 1. GETH driver testing and reference demo applications in pre silicon environments like Virtual Prototype model and Cadence Simulator.
• 2. Provide consultations for SOC-Verification and MCAL Driver Development and Validation.
• 3. Provide critical feedback to concept.
• 4. Support Perspec based validation of GETH

Aug 2018 – Sep 2020 · 2 yrs 1 mo

• 1. Bare Metal Device Driver Development, Validation, Stress Testing, Demo app development and Maintenance for ASCLIN (UART, LIN, SPI), QSPI, SENT, I2C and other low speed COMM peripherals of Aurix A2G and A1G.
• 2. Python scripting for multiple PoCs and automation projects.
• Aurix 3rd Gen project begins Aug 2019.
• 1. Porting of 8 legacy low speed COMM drivers for Aurix 3rd Gen Microcontrollers.
• 2. New feature development for HSSL and MCAN.
• 3. S/w Architecture and Driver Development, Testing and Demos for CAN Routing Engine (CRE) and Data Routing Engine (DRE).
• 4. Ethernet Basic Communication Stack: S/w Architecture, Driver Development for Synopsis IP XGMAC, also called Gigabit Ethernet (GETH) a high speed comm peripheral in Aurix 3rd Gen microcontrollers. Layers include DMA, MTL, MAC, Bridge, S/w services and comm stack.
• 5. Testing on pre-silicon environments like Virtual Prototype model.