Toan Tran

Software Engineer

Ho Chi Minh City, Vietnam6 yrs 1 mo experience

Key Highlights

  • Expert in Design Verification and ASIC Design.
  • Proficient in UVM and Gate Level Simulation.
  • Strong background in Hardware Verification for MCUs.
Stackforce AI infers this person is a Semiconductor Design Verification Engineer with expertise in ASIC and MCU verification.

Contact

LinkedIn

Skills

Core Skills

Design VerificationVerification PlanningAsic DesignSimulationHardware Verification

Other Skills

VerilogSystemVerilogUVMCoverage AnalysisGate Level SimulationPower AnalysisAssembly LanguageMicrocontrollersCshellEnglishC++C (Programming Language)

Experience

6 yrs 1 mo
Total Experience
2 yrs 5 mos
Average Tenure
1 yr 2 mos
Current Experience

Astera labs

Senior Design Verification Engineer

Apr 2025 – Present · 1 yr 2 mos · Ho Chi Minh City, Vietnam · On-site

  • Ethernet PCS/PMA IP:
  • Block level: AM (Alignment Marker) Alignment
  • Investigate IEEE standard and design document for incharge module: AM(Alignment Markers) Alignment
  • Make verification plan, check items.
  • Build UVM environment from scratch to verify the module.
  • Run coverage and confirm.
  • PCS/PMA Top level:
  • Define the verification item of incharge block level for Top level and verify.
  • Do verification for incharge items: update/add more sequences/testcase.
  • Analyze and confirm coverage for PCS/PMA IP.
  • QSPI slave IP:
  • the IP have QSPI standard interface and output APB Master interface for writing/reading CSR.
  • Do full flow verification for this IP
VerilogSystemVerilogUVMCoverage AnalysisDesign VerificationVerification Planning

Synopsys inc

ASIC Digital Design Engineer

Sep 2022 – Mar 2025 · 2 yrs 6 mos · Ho Chi Minh City, Vietnam

  • Mainly in charge of Gate level simulation task on HBM3 PHY IP product line:
  • Use UVM to verify the design at gate level.
  • Run Gate level simulation with post-layout netlist and SDF annotation.
  • Debug the failure related to timing violation, testbench/checker issue,
  • cases that in RTL simulation cannot detect.
  • Develop testcase for Power Analysis:
  • Create test scenerio to simulate the worst case of design and release VCD
  • le for Power Analysis team.
  • Analyze the result if there is any problem, and explain if the result is
  • expected
UVMGate Level SimulationPower AnalysisASIC DesignSimulation

Renesas design vietnam co., ltd.

Hardware Engineer

Mar 2020 – Aug 2022 · 2 yrs 5 mos · Ho Chi Minh City, Vietnam

  • Mainly in charge of veri cation IPs in MCU: Temper sensor, Timer, CRC
  • calculator
  • Connect IPs to MCU system.
  • Make test plan for IPs.
  • Verify IPs in MCU system by assembly code
Assembly LanguageMicrocontrollersHardware Verification

Education

University of Information Technology

Bachelor of Engineering - BE — Computer Engineering

Stackforce found 100+ more professionals with Design Verification & Verification Planning

Explore similar profiles based on matching skills and experience

Rajendra Prasad

Rajendra Prasad

R&D Engineering Director

at Synopsys Inc

Mountain View, United States27 yrs 2 mos exp
ManagementMachine LearningLeadershipCustomer EngagementPeople Management
CHANDAN JHA

CHANDAN JHA

Senior Hardware Engineer

at Qualcomm

Bengaluru, India5 yrs 9 mos exp
Physical DesignMicroarchitecture
Prakash Mishra (प्रकाश मिश्रा)

Prakash Mishra (प्रकाश मिश्रा)

Staff Engineer

at Synopsys Inc

Hyderabad, India7 yrs 11 mos exp
Analog Circuit DesignLow-power Design
Ajitesh Mishra

Ajitesh Mishra

Senior Engineer

at Sandisk

Bengaluru, India7 yrs exp
Application-Specific Integrated Circuits (ASIC)Hardware EngineeringFunctional VerificationSAPDevOps
Allen Nguyen

Allen Nguyen

SOC Physical Design Engineer

at Synopsys Inc

Ho Chi Minh City, Vietnam5 yrs 3 mos exp
Physical DesignApplication-Specific Integrated Circuits (ASIC)
Srinath Jeevakumar

Srinath Jeevakumar

Senior Architect

at NVIDIA

Bengaluru, India6 yrs 8 mos exp
Performance VerificationSilicon Bring-upPerformance Analysis
Amit Ranjan

Amit Ranjan

Senior Research And Development Engineer

at Tejas Networks

Nalanda, India8 yrs 10 mos exp
Hardware EngineeringElectronics Hardware Design
Shripad Deshpande

Shripad Deshpande

Head of R&D - Hardware Design and EDA

at Chipforge.ai

India27 yrs 2 mos exp
EDASoCVirtual PrototypingASIPRTL design