VIGNESH IYER R. — CEO

As a Design Verification Engineer, I am keen on applying my skills and knowledge in digital electronics, ASIC Verification, and VLSI to verify the functionality and performance of various RTL designs and protocols. I have good knowledge on Verilog, System Verilog, UVM and Perl Scripting. I have hands-on experience in Protocol Verification like APB, UART, SPI, and Ethernet IP using SV and UVM Environment as well as Perl scripting. I have worked on PCIe Protocol and PIPE Interface for the Enhancing Communication Protocol Knowledge. Currently working on HPC SoC Memory Mapping, where I gained knowledge of the flow of the Data from one Subsystem to other inside a SoC. Currently Upgrading my skills Python Scripting for efficient Verification Strategies. I graduated with a Bachelor of Technology degree in Electronics and Communications Engineering from Malla Reddy College of Engineering & Technology in 2022, where I gained a broad knowledge of engineering concepts and participated in several certification courses and hackathons with my team. I also completed a six-month internship at Electronics Corporation of India Ltd. (ECIL), where I learned how to apply engineering concepts to systems and processes in both defense and private industries. I am passionate about innovation, supportive of my peers, and enthusiastic about learning new things. My goal is to become an expert in the field of electronics and communication engineering and achieve greater positions.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC and VLSI methodologies.

Location: Hyderabad, Telangana, India

Experience: 3 yrs 2 mos