Akhil Sariki

Software Engineer

Visakhapatnam, Andhra Pradesh, India2 yrs 11 mos experience
Highly Stable

Key Highlights

  • Expertise in Physical Design and verification flows.
  • Proficient in Static Timing Analysis and Reliability verification.
  • Hands-on experience in healthcare technology projects.
Stackforce AI infers this person is a VLSI Design Engineer with a focus on healthcare technology and physical design.

Contact

Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

crosstalk analysisDRC/LVS clean upReliability & IR verificationTCLPythonDesign EngineeringSynopsys PrimetimeDesign Rule Checking (DRC)Application-Specific Integrated Circuits (ASIC)Logic DesignTransistorsCircuitTimingCMOSPlace & Route

About

Currently working as SOC Design Intern at Intel (XEG Business group). Have good expertise in Physical Design and verification flows from RTL to GDSII with 7nm technology node. Proficient in Static Timing Analysis, crosstalk analysis, DRC/LVS clean up, and Reliability & IR verification. Skilled in using Synopsis Fusion Compiler ,Prime Time and ICV, as well as scripting with TCL and Python. Previously, contributed to innovative projects at Innovation Design Quotient, focusing on healthcare devices and oral screening systems. Hands-on experience in interface designing using Apache Cordova framework (Web application Designing) and booting special microprocessors for healthcare devices. Skills: Strong knowledge of C, Verilog, Python, TCL, JavaScript, Fusion Compiler, Prime Time, Xilinx ISE, Silvaco, and MATLAB. Passionate about digital logic design and analog VLSI circuits.

Experience

2 yrs 11 mos
Total Experience
2 yrs 11 mos
Average Tenure
2 yrs 11 mos
Current Experience

Synopsys inc

2 roles

Staff Engineer

May 2026Present · 1 mo · On-site

Senior Engineer

Jul 2023May 2026 · 2 yrs 10 mos · On-site

Intel corporation

SOC Design Intern

Jun 2022Jun 2023 · 1 yr · Bengaluru, Karnataka, India · On-site

  • - Worked as an intern in the SOC Structural Design Team in XEG department.
Physical DesignStatic Timing Analysiscrosstalk analysisDRC/LVS clean upReliability & IR verificationTCL+1

Indq

Intern

May 2019Oct 2019 · 5 mos · Vishakhapatnam Area, India

  • - Worked on development of novel assistive technologies for differently-abled .

Education

Dr. B R Ambedkar National Institute of Technology, Jalandhar ( PUNJAB)

Master of Technology - MTech — VLSI Design

Sep 2021Jun 2023

Indian Institute of Information Technology Design & Manufacturing Kancheepuram

Bachelor of Technology - BTech — Electronics and Communication Engineering

Jan 2016Jan 2020

Ascent Classes

Higher Secondary education

Jan 2014Jan 2016

Jawahar Navodaya Vidyalaya - JNV

Secondary Education

Jan 2010Jan 2014

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