Dilraj Ck

Software Engineer

Bengaluru, Karnataka, India5 yrs 6 mos experience
Highly Stable

Key Highlights

  • Expert in static timing analysis and verification.
  • Proficient in Verilog and TCL scripting.
  • Strong background in digital and analog circuit design.
Stackforce AI infers this person is a highly skilled engineer in VLSI and ASIC design.

Contact

Skills

Core Skills

Static Timing AnalysisVerilog

Other Skills

PrimetimeTCLSPICEH-SpiceDistributed STAC++EngineeringC (Programming Language)LeadershipEmbedded SystemsDigital ElectronicsCircuit DesignField-Programmable Gate Arrays (FPGA)Application-Specific Integrated Circuits (ASIC)Logic Synthesis

Experience

5 yrs 6 mos
Total Experience
5 yrs 6 mos
Average Tenure
5 yrs 6 mos
Current Experience

Synopsys inc

4 roles

Staff Engineer

Promoted

Jan 2025Present · 1 yr 5 mos

Senior Engineer

Jan 2024Jan 2025 · 1 yr

Application Engineer II

Nov 2020Dec 2023 · 3 yrs 1 mo

PrimetimeTCLStatic Timing AnalysisSPICEH-SpiceVerilog+1

Technical Intern

Feb 2020Nov 2020 · 9 mos

PrimetimeTCL

Education

National Institute of Technology Calicut

Master's degree — ELECTRONIC DESIGN AND TECHNOLOGY

Jan 2017Jan 2019

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