Dec 2019 – Sep 2020 · 9 mos · Hsinchu Metropolitan Area

• Computer architecture and performance analysis
• Sampling the representative subsets for the long run benchmarks (spec2017, ...)
• Deep-dive to the large benchmark program and analyze the performance.
• Start from overall algorithm study, dive into the block with a performance issue.
• Studied cases: Antutu: 2D physics for collision detection, Huffman coding, gzip, ...

Jul 2017 – Dec 2019 · 2 yrs 5 mos · Hsinchu Metropolitan Area

• Design Flow and Methodology Development for 10nm, 7nm, 5nm, 3nm.
• TSMC Internal Evaluation Tool Development for standard cell library, APR tool, design rule co-design.
• LEF DEF LIB GDS parser/editor with new syntax support.
• Graphical cell pin access layout viewer with design rule support development.
• Design Methodology Development
• Context-aware Cell Leakage Calculation Methodology with multi-voltage domains support.
• Provide GDS flow utility to customers(Apple, ...).
• Enable PrimeTimePX for this feature, generate golden by hands-on code for the algorithm and verify the result.
• Cell internal metal coloring methodology development.
• Ring-oscillator based cell timing calculator.

Aug 2014 – Nov 2016 · 2 yrs 3 mos · Hsinchu Metropolitan Area

• Design Flow and Methodology Development for 10nm , 7nm.
• Design rule enablement.
• Enable EDA tool with the latest process design rule support with Floorplan/Placement/Routing/RC/EM and user-friendly/robustness co-considered spec.
• TSMC inter-college program(JDP) for methodology development.
• Develop realistic needs and future encountered problems for college study.
• Contact person to connect college for the topic with Prof. Ting-Chi Wang and Prof. Wai-Kei Mak in NTHU.
• Corporate with process RD, standard cell designers, IP designers, and DRC team to define and review design rule.
• IP & Chip Integration Guideline for Design Rule Constraint Violation Prevention for Standard cell, Macro, APR pin access, routing consideration.

Nov 2016 – Jul 2017 · 8 mos · Hsinchu Metropolitan Area

• AI Chip Simulator Development
• Develop functional model for AI processor for the Matrix Multiplier.
• VLIW Assembly writing and tuning to gain better performance for AI processor.