Jim Lo

DevOps Engineer

Taipei, Taipei City, Taiwan13 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in RTL design and DDR integration
Proven track record in silicon debugging
Strong experience in SoC design and verification

Stackforce AI infers this person is a highly skilled engineer in semiconductor design and verification.

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Skills

Core Skills

Rtl DesignDdr IntegrationMbist ImplementationSoc DesignIp VerificationSilicon Debugging

Other Skills

simulation debuggingSDR BIST maintenanceDDR2/DDR3 integrationSerdes IP maintenanceAvalon-mm to AMBA bridge developmentTCON development on FPGAIP test implementationIP QAsimulationSTAsynthesisLECDDR IP supportsilicon debugsimulation debug

Experience

13 yrs 6 mos

Total Experience

2 yrs 8 mos

Average Tenure

5 yrs 9 mos

Current Experience

新思科技股份有限公司

Sr Staff engineer

Sep 2020 – Present · 5 yrs 9 mos · 台灣臺北市 · Hybrid

Helping the enterprise customers to implement their DDR/Low power DDR/HBM design from RTL level to silicon level, also including simulation debugging and silicon debugging etc.

RTL designDDR integrationsilicon debuggingsimulation debugging

Raydium semi-conductor corp

Deputy Manager

Feb 2018 – Sep 2020 · 2 yrs 7 mos · 台灣臺北市 · On-site

Tcon R&D
maintain SDR BIST.
DDR2/DDR3 integration.
Serdes IP: maintain LVDS RX.
Pixel quality design: maintain Line OD.
MBIST implementation.
Assist to develop Avalon-mm to AMBA bridge (AXI and AHB).
Assist to develop TCON on Stratix V/ Arria 10 FPGA.

SDR BIST maintenanceDDR2/DDR3 integrationSerdes IP maintenanceMBIST implementationAvalon-mm to AMBA bridge developmentTCON development on FPGA+1

Global unichip

SoC Design Engineer

Jul 2016 – Feb 2018 · 1 yr 7 mos · 台灣 Taiwan 新竹市 · On-site

In charge of IP test implementation for SOC and do IP QA, also do simulation, STA, synthesis and LEC for IP verification.
Implement PCIe, DLL and Efuse test function for customer’s SoC.
Generated CP/FT pattern for manufacture testing, also debug with test engineer for the delivered CP/FT pattern.

IP test implementationIP QAsimulationSTAsynthesisLEC+2

智原科技

DDR FAE

Mar 2015 – Jul 2016 · 1 yr 4 mos · 台灣 Taiwan 新竹市 · On-site

DDR IP support customer, which containing DDR silicon debug, simulation debug, integration with DDR controller and PHY, synthesis and LEC FORMAL.
Supported over 12 projects in 1.4 years, which including Japan tier 1 image chip vendor, China tier 1 telecommunications vendor.

DDR IP supportsilicon debugsimulation debugintegration with DDR controller and PHYsynthesisLEC FORMAL+2

威盛電子股份有限公司

SoC Design Engineer

Dec 2012 – Mar 2015 · 2 yrs 3 mos · 台灣新北市 · On-site

Maintained and implement MBIST flow.
In charge of verification of IP's function test, assist in the build-up test bench IP's function test, generating test pattern for ATE.
Supported 3 SOC projects in 3 years.

MBIST flow maintenanceIP function test verificationtest bench assistancetest pattern generationMBIST implementationSoC design