Parth Saxena

Software Engineer

Bengaluru, Karnataka, India8 yrs 7 mos experience
Highly Stable

Key Highlights

  • Expert in ASIC design verification methodologies.
  • Proficient in SystemVerilog and UVM for robust testing.
  • Strong leadership in cross-functional engineering teams.
Stackforce AI infers this person is a Design Verification Engineer specializing in ASIC and SoC technologies.

Contact

LinkedIn

Skills

Core Skills

Design Verification TestingSystemverilogIp Verification

Other Skills

Application-Specific Integrated Circuits (ASIC)Leadershipcoverage code + functional + UNRCommunicationSystem on a Chip (SoC)Interpersonal SkillsTest StrategyIEEE 802.11Functional Verification802.11aUniversal Verification Methodology (UVM)VerdiInterpersonal CommunicationCode CoverageGate Level Simulation

About

I am working as a Design Verification Engineer in Qualcomm, Focus area in my job is to prepare the verification plan, implement an automated scoreboard/reference model based testbench according to the plan, adding completely randomised test scenarios and write detailed functional coverage for robust verification. Also use tools like formal verification to ensure no bugs.

Experience

8 yrs 7 mos
Total Experience
8 yrs 2 mos
Average Tenure
5 mos
Current Experience

Nvidia

Senior Design Verification Engineer

Jan 2026 – Present · 5 mos · Bengaluru · On-site

SystemVerilogDesign Verification TestingApplication-Specific Integrated Circuits (ASIC)

Qualcomm

4 roles

Staff Engineer

Nov 2025 – Jan 2026 · 2 mos

LeadershipIP Verificationcoverage code + functional + UNRSystemVerilogCommunicationSystem on a Chip (SoC)+22

Senior Lead Engineer

Promoted

Nov 2022 – Oct 2025 · 2 yrs 11 mos

IP Verificationcoverage code + functional + UNRSystemVerilogCommunicationSystem on a Chip (SoC)Interpersonal Skills+20

Senior Hardware Engineer

Promoted

Dec 2019 – Nov 2022 · 2 yrs 11 mos

IP Verificationcoverage code + functional + UNRSystemVerilogCommunicationSystem on a Chip (SoC)Interpersonal Skills+18

Engineer

Aug 2017 – Dec 2019 · 2 yrs 4 mos

  • SoC/HW - VLSI
IP Verificationcoverage code + functional + UNRSystemVerilogCommunicationSystem on a Chip (SoC)Interpersonal Skills+17

Education

Indian Institute of Technology, Delhi

Master’s Degree — Optoelectronics and Communication

Jan 2015 – Jan 2017

Swami Keshwanand Inst. Of Tech. Mgt. & Gramothan,Jaipur

Bachelor of Technology (B.Tech.)

Jan 2010 – Jan 2014

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