Lokesh Babu Pundreeka

CEO

Bengaluru, Karnataka, India25 yrs 3 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Over two decades of expertise in digital hardware design.
  • Led multi-million global projects in verification.
  • Proven track record in client success and innovation.
Stackforce AI infers this person is a leader in digital hardware design and verification within the semiconductor industry.

Contact

Skills

Core Skills

LeadershipAccount ManagementComputer HardwareUniversal Verification Methodology (uvm)Digital Designs

Other Skills

Organizational LeadershipAMBA AHBARM Cortex-MFormal VerificationLow PowerEmulationAutomotive-Functional Safety (ISO 26262)AssertionBasedVerification(ABV)USBLowPower(LP)VerificationCPFVerificationSystemVerilogLow-power DesignARM

About

Astute Design and Verification Leader | Director AE-System Verification Group | 2 Decades of Expertise Seasoned professional with over two decades of expertise in digital hardware design and verification, specializing in project management, EDA, ASIC, IP, SOC, Front-end Design, ARM, ABV, Low Power, Formal Verification, Emulation, and Automotive-Functional Safety (ISO 26262). As the Director AE-System Verification Group at Cadence Design Systems, I lead a team of 40+ Technical Pre-sales engineers and senior managers, steering innovation in Systems, Design, Advanced Verification, and Validation. Renowned for spearheading multi-million global projects and implementing process improvements across project management, quality assurance, customer support, and systems engineering. My transformative and visionary leadership history involves leading teams through market shifts, establishing strong organizational visions, fostering innovation, and building high-performance teams. Proven track record in delivering client success and projects with out-of-the-box technical solutions. Expertise extends to cross-cultural project management, technical marketing, and continuous improvement. Skills encompass vision, strategy, growth, AE management, technical sales, and resource optimization. Committed to client-focused strategies, ensuring the timely delivery of high-quality products and services. Valuable asset in the field of digital hardware design and verification.

Experience

25 yrs 3 mos
Total Experience
12 yrs 7 mos
Average Tenure
20 yrs
Current Experience

Cadence design systems

6 roles

Group director Application engineering

Jul 2023Present · 2 yrs 11 mos

Account ManagementLeadershipOrganizational Leadership

Director AE , System Verification Group

Promoted

May 2017Aug 2023 · 6 yrs 3 mos

AMBA AHBComputer HardwareLeadership

Sr. Staff AE / Technical Director

Jul 2016Apr 2017 · 9 mos

  • Responsibilities:
  • Manage Jasper Gold AE team for India Region and also work with Sales and account team for Business development.
  • Drive Automotive Functional Safety Solution (ISO 26262) for India Region.
  • Work with Key Customer in India for adopting emerging Verification Solutions.
Universal Verification Methodology (UVM)AMBA AHBDigital DesignsComputer HardwareARM Cortex-M

Staff Application Engineer/Sr. Technical Lead

Promoted

Jul 2012Jun 2016 · 3 yrs 11 mos

  • Responsible for
  • Leading the Verification Solution initiative across India by partnering with Account team and RnD and help in creating new opportunities specifically in Low Power, Automotive & Safety and Performance Area's.
  • Account Lead
  • Mentor new hires and make them specialized pre-sales AE to face any verification challenges at various customers places.
Universal Verification Methodology (UVM)AMBA AHBDigital DesignsComputer HardwareARM Cortex-M

Sales Technical Leader

Jul 2010Jul 2012 · 2 yrs

  • Responsible for Driving following technologies for India .
  • + ABV solutions like formalverification, Semi-formal verification and Simulation.
  • + Low power Verification based on CPF and UPF power intent
Universal Verification Methodology (UVM)Digital DesignsComputer Hardware

Lead Services Application Engineer

Apr 2006Jul 2010 · 4 yrs 3 mos

  • + Assertion based Verification[ABV]
  • + Formal/Property verification
  • + Lowpower verification
  • + Functional and code coverage
  • + Verification Planning
Universal Verification Methodology (UVM)Digital DesignsComputer Hardware

Tii

2 roles

Senior Design Engineer

Promoted

Jun 2003Mar 2006 · 2 yrs 9 mos

  • + Design
  • + IP/SoC verification
  • + Validation
  • + Silicon Debug
Digital DesignsComputer Hardware

Design Engineer

Sep 2000Mar 2003 · 2 yrs 6 mos

  • + Specman ["e"] Environment and testcase development.
  • + IP Verification
  • + Timing Simulations
  • + Part of TI Next Generation Emulation Device and 802.11a/b/g
  • Baseband Processors design and Verification
  • + Test Vectors generation for Silicon Debugging [TDL's]

Education

Birla Institute of Technology and Science, Pilani

MS[DLP] — Micro Electronics

Jan 2004Jan 2006

Osmania University

B.E — Electronics & Communication

Jan 1996Jan 2000

A.P.Board of Technical Education And Training, Hyderabad

Diploma — Electronics & Communication

Jan 1993Jan 1996

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