Vineet Dubey

Software Engineer

Bengaluru, Karnataka, India12 yrs 9 mos experience

Key Highlights

Expert in VLSI design and verification methodologies.
Hands-on experience with RTL design and FPGA flows.
Proficient in debugging and verification technologies.

Stackforce AI infers this person is a VLSI Design and Verification Engineer with expertise in digital design.

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Skills

Core Skills

DebuggingVerification TechnologiesPerformance ImprovementDigital Circuit Design

Other Skills

VCS technologiesProject environment deploymentTrainingVCSFPGAVerilogSystemVerilogUniversal Verification Methodology (UVM)SimulationsShell ScriptingAdventure TravelMicrosoft ExcelPowerPointEmbedded CMatlab

About

I am passionate about VLSI design and verification. I have a hand on knowledge of RTL design, STA, Clock domain crossing, FPGA flow. also, created verification environment with SV Testbench for my master's final thesis. I have taken training in UVM.

Experience

12 yrs 9 mos

Total Experience

2 yrs 5 mos

Average Tenure

1 yr 11 mos

Current Experience

Synopsys inc

Staff Engineer

Jul 2024 – Present · 1 yr 11 mos · Bengaluru, Karnataka, India · On-site

Samsung semiconductor

Staff Engineer

Mar 2024 – Jan 2025 · 10 mos · Bengaluru, Karnataka, India · Hybrid

Intel corporation

CAD Engineer

Dec 2021 – Feb 2024 · 2 yrs 2 mos · Bengaluru, Karnataka, India · Hybrid

Providing Front-end CAD Support for all the on-going projects in Intel.
Deploying and automating the VCS technologies like Partition Compile, Save-restore, DTL, DPO on various projects to
simplify the usage.
Closely working with RTL Designers and Verification engineers in debugging the various design and/or tool issues
reported during migration like Race, Time-Zero hang/loop, Simulation mismatch.
Helping user to understand the various verification technologies like Xprop, NLP, SDF, Partition Compile, DTL, ICO, SVA,
Constraints, Encryption.
Deploying the new Intel Specific Project environment (Cheetah Flow) to all the new and existing projects.
Created multiple flow specific documents for all the frontend flows.
Providing multiple training sessions to different project teams on all the compilation and simulation performance
improvement techniques and flows.

VCS technologiesDebuggingVerification technologiesProject environment deploymentTraining

Synopsys inc

2 roles

Application Engineer 2

Aug 2018 – Dec 2021 · 3 yrs 4 mos

 Providing the pre and post – sales technical supports during the installation and maintenance of VCS, DVE and
Verdi tool.
 Working closely with AMD CAD team as Contract Employee for VCS and Verdi related issues from past 2.5
years
 Debugging the design from customer and tool issue reported during migration for issues like Race, Time-Zero
hang /loop, Simulation mismatch.
 Worked on multiple projects from AMD for Performance issue at compile and simulation.
 Worked on various technologies like Partition Compile, Xprop, Constraint, SVA, Low Power debug, SDF
annotation.
 Re-creating the issue in small testcase after debugging it from Customer Design.

VCSDebuggingPerformance improvementVerification technologies

Technical Intern

Jul 2017 – Jul 2018 · 1 yr

Unistring tech solutions pvt ltd (uts)

Intern

Jul 2017 – Jul 2017 · 0 mo · Greater Hyderabad Area

At university of hyderabad

PG Student

Jul 2016 – Jun 2018 · 1 yr 11 mos · Hyderabad Area, India

Master of Technology program in Integrated Circuit Technology at University of Hyderabad is focusing on the mainly :- Digital Circuit Design and Testing, Microelectronics device Fabrication and Testing, RF and Microwave design and testing.
Activities :-
organised workshop on RPi 3 B+;
MESFET fabrication with gate length 10 um in University clean room;
implementation of uart on the spartan 3E FPGA board;
LCD implementation on the spartan 3E.