PREM KUMAR KARRI

Product Engineer

Visakhapatnam, Andhra Pradesh, India4 yrs 9 mos experience

Key Highlights

  • Expert in advanced node analog layout design.
  • Proficient in DRC/LVS closure and physical verification.
  • Strong background in custom layout and electromigration awareness.
Stackforce AI infers this person is an Analog Layout Design Engineer specializing in advanced semiconductor technologies.

Contact

Skills

Core Skills

Analog Layout DesignPhysical Verification

Other Skills

Calibre DRC/LVSMatching & Symmetry TechniquesInterconnect ReliabilityAnalog Block LayoutLVS DebuggingDRC DebuggingAnalog CircuitsSignal IntegrityPower ElectronicsCircuit DebuggingPower Distribution / IR Drop BasicsTCLLinuxPLL LayoutBGR Layout

About

I’m an Analog Layout Design Engineer with 4+ years of experience working across advanced nodes like 16nm, 7nm, 5nm, and 3nm.I specialize in custom layout, device-level understanding, and physical verification.My work involves block-level layout, matching strategies, electromigration awareness, and DRC/LVS closure.I focus on solving layout challenges, optimizing routing, and delivering reliable layouts optimized for performance, area, and reliability.Skills:• Custom Layout (Analog/Mixed-Signal)• Advanced Nodes: 16nm, 7nm, 5nm, 3nm• Floorplanning, Placement, Routing• MOSFET, FinFET & GAA Layout• Tools: Cadence Virtuoso, Calibre, ICV, Totem RV• EM/IR Awareness & Layout Reliability• Linux, Windows, Mac

Experience

4 yrs 9 mos
Total Experience
2 yrs 11 mos
Average Tenure
1 yr 11 mos
Current Experience

Insemi technology services pvt. ltd.

Senior Analog Layout Engineer

Jul 2024Present · 1 yr 11 mos · Bengaluru, Karnataka, India · On-site

  • Working as custom layout engineer for Analog/Mixed-Signal blocks.
  • Handling block-level layout, device matching, symmetry, shielding, guard rings.
  • Working across multiple advanced nodes.
  • Responsible for DRC/LVS closure, extraction checks, and physical verification.
  • Collaborating with design teams and delivering quality layouts.
Analog Layout DesignPhysical Verification

Capgemini engineering

Analog Layout Engineer

Sep 2021Aug 2024 · 2 yrs 11 mos · Bangalore Urban, Karnataka, India

  • Delivered layout for 7nm and 5nm analog blocks.
  • Handled on routing, floorplanning, reliability constraints and marker checks.
  • Responsible for DRC, LVS, and extraction closure.
  • Experienced in standard nodes and advanced FinFET & GaaFET layout practices.
Physical VerificationAnalog Layout Design

Education

Nadimpalli Satya Narayana Raju Institute of Technology

Bachelor of Technology - BTech — Electrical and Electronics Engineering

Jun 2017Aug 2020

Mrs A.V.N. College - India

Diploma of Education — Electrical and Electronics Engineering

May 2013Jun 2016

A.M.G REM HIGH SCHOOL

SSC — 10th Class

May 2012May 2013

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