B Naveen kumar

CEO

Seoul, Incheon, South Korea7 yrs experience

Highly StableAI Enabled

Key Highlights

Expert in Physical Design and Timing Closure.
Proficient in Low-power Design and CPU implementation.
Experienced with Fusion Compiler and High Performance Computing.

Stackforce AI infers this person is a Physical Design Engineer specializing in VLSI and ASIC development.

Contact

Skills

Core Skills

Timing ClosureLow-power DesignCpu Design

Other Skills

DESIGN PLANNINGHierarchical flowCSU/DSUsMSCTSPlace & RouteTimingHigh Performance Computing (HPC)Clock meshPower AnalysisIndesign ppFmax pushfusion compilerStatic Timing AnalysisDSO.aiclock tree synthesis (CTS)

About

Looking for a challenging job in physical design domain

Experience

7 yrs

Total Experience

3 yrs 4 mos

Average Tenure

4 mos

Current Experience

Cadence

Lead Application Engineer

Feb 2026 – Present · 4 mos · Hyderabad, Telangana, India · On-site

Synopsys inc

4 roles

Staff Applications Engineer

Jan 2024 – Jan 2026 · 2 yrs · On-site

Handling PnR for DSU and CPU to meet PPA
using Fusion compiler

Timing ClosureLow-power DesignDESIGN PLANNINGHierarchical flowCSU/DSUsMSCTS+1

Applications Engineer II

Dec 2021 – Jan 2024 · 2 yrs 1 mo · On-site

Working on Hierarchical ARM ELP Core CPU Implementation (Samsung 3nm) using Fusion compiler.

TimingTiming ClosureHigh Performance Computing (HPC)DesignPlanningMsctsClock mesh+5

Applications Engineer I

Mar 2020 – Dec 2021 · 1 yr 9 mos · On-site

Worked on Hierarchical ARM ELP core CPU PnR implementation (Samsung 4nm), Achieving target Fmax and Timing closure in Fusion compiler.
Low power implementation on ARM ELP core CPU.
FC-PT timing correlation

fusion compilerStatic Timing AnalysisTimingTiming ClosureHigh Performance Computing (HPC)DSO.ai+3