Veeranjaneyulu . — Product Engineer

I am an ASIC STA & Physical-Aware Synthesis Engineer with 2+ years of experience, currently working in a product-based environment on Qualcomm SoC designs. My core expertise lies in block-level Static Timing Analysis (STA), timing constraint development, and timing closure across multiple modes, corners, and advanced technology nodes (TSMC N2FF, 14nm, 22nm). I have hands-on experience with MCMM analysis, OCV/AOCV, Statistical Timing, and Signal Integrity effects. I have actively worked on timing ECO generation and collaborated closely with Physical Design teams to deliver placement- and routing-friendly ECO solutions, enabling efficient timing convergence. My experience also includes logical-aware and physical-aware synthesis, CLP/VCLP clean netlist generation, and low-power design techniques such as clock gating, power gating, and multi-voltage designs. I have performed power analysis using PrimeTime PX (PTPX) and handled UPF/MV issue resolution across synthesis and PNR stages. I am proficient in Synopsys toolchains including Design Compiler, Fusion Compiler, PrimeTime, PrimeTime PX (PTPX), and ICC2, and I actively use Tcl and shell scripting to automate STA, synthesis, and power analysis flows. I am passionate about solving deep timing and low-power challenges and am actively seeking ASIC STA / Timing Closure / Physical-Aware roles in semiconductor companies.

Stackforce AI infers this person is a Semiconductor Design Engineer specializing in ASIC and low-power design methodologies.

Location: Bengaluru, Karnataka, India

Experience: 2 yrs 1 mo