SRIKANTH Manchi — Software Engineer

Block level Scan Insertion , Able to implement different Scan Compression Techniques, On -Chip Clock controller (OCC), Wrapper Insertion / IEEE 1500, Standard JTAG Protocol, ATPG pattern generation for different fault models like Stuckat / DC , At-speed fault models like transition and Path delay fault models. No-Timing ATPG simulations / pattern validation for Block level.

Stackforce AI infers this person is a DFT and ATPG specialist in the semiconductor industry.

Location: Bengaluru, Karnataka, India

Experience: 11 yrs 1 mo