SRIKANTH Manchi — Software Engineer
Block level Scan Insertion , Able to implement different Scan Compression Techniques, On -Chip Clock controller (OCC), Wrapper Insertion / IEEE 1500, Standard JTAG Protocol, ATPG pattern generation for different fault models like Stuckat / DC , At-speed fault models like transition and Path delay fault models. No-Timing ATPG simulations / pattern validation for Block level.
Stackforce AI infers this person is a DFT and ATPG specialist in the semiconductor industry.
Location: Bengaluru, Karnataka, India
Experience: 11 yrs 1 mo
Skills
- Atpg
- Dft
Career Highlights
- Expert in DFT and ATPG methodologies.
- Proficient in implementing Scan Compression Techniques.
- Experienced in digital electronics and simulations.
Work Experience
Samsung Semiconductor
Staff Engineer (1 yr)
Achronix Semiconductor Corporation
Senior Engineer (1 yr 2 mos)
AISemiCon
Lead Engineer (8 mos)
STMicroelectronics
Technical Lead (1 yr 9 mos)
Tessolve
Design Engineer (2 yrs 3 mos)
American Express Global Business Travel
Senior Analyst (2 yrs 1 mo)
SAP Concur
Techical Consultant (2 yrs 2 mos)
Education
Master of Technology (MTech) at MSRAMAIAH INSTITUE OF TECHNOLOGY
B.Tech at Acharya Nagarjuna University
Intermediate at Sri Chaitanya Junior college
SSC at KAKATIYA RESEDENTIAL SCHOOL