Yuvaraj Siddani — Product Engineer
🔧 Physical Design Engineer | ASIC Back-End | Synopsys Suite | 14nm & 28nm I am a Physical Design Engineer with certified hands-on training in the complete ASIC back-end flow — from RTL netlist to GDSII signoff. I work on industry-standard Synopsys EDA tools across 14nm and 28nm technology nodes, with practical experience on multi-clock, multi-macro designs targeting frequencies up to 1 GHz. 🛠 What I Do: ▸ Floorplanning, power planning, placement, CTS, routing, timing closure, and physical verification ▸ SDC constraint authoring for multi-clock domains and complex netlists ▸ Power mesh design targeting IR-drop budgets; PG connectivity and DRC resolution ▸ Setup/hold slack closure using PrimeTime STA across multi-corner, multi-mode scenarios ▸ DRC & LVS signoff using IC Validator at both 14nm and 28nm nodes 📐 Key Projects: ▸ J-BUS Interface (14nm, 9M, 86 macros, 36K cells): Closed timing at 699 MHz & 833 MHz ▸ DTMF (28nm, 8-clock design): Achieved clean signoff at 1 GHz target ▸ Falcon (28nm, 3-clock): Full PD flow from floorplan to LVS/DRC signoff at 500 MHz 📍 Actively seeking Physical Design / STA Engineer roles in Bengaluru, Hyderabad, or Noida. 📬 Reach me: ssyj4486@gmail.com | 6303308554 | siddani-design-folio.lovable.app
Stackforce AI infers this person is a Semiconductor Physical Design Engineer with expertise in ASIC back-end processes.
Location: Bengaluru, Karnataka, India
Experience: 0 mo
Skills
- Physical Design
- Static Timing Analysis
- Timing Closure
Career Highlights
- Expert in ASIC physical design with Synopsys tools.
- Proven track record in timing closure and signoff.
- Hands-on experience with complex multi-clock designs.
Work Experience
ChipEdge
Physical Design Engineer (7 mos)
Education
Bachelor of Technology - BTech at Audisankara College of EducationNH-5, Bypass Road, Aravinda Nagar,Gudur
