Darshan KS — Software Engineer
•Good knowledge and understanding of the VLSI Design Flow in all aspects. •Strong conceptual understanding and practical experience in the physical design flow of an ASIC, including floorplanning, power planning,placement, CTS, routing, and signoff 40nm technology. •Aware of Signal Integrity (SI) issues like Crosstalk, Reliability issues like EM, and Antenna Effect. •Static Timing Analysis (STA): Experience in fixing setup and hold violations, identifying timing exceptions, timing closure, and effects ofclock skew on timing and timing analysis of latches. •Good understanding of TCL scripting, shell scripting,perl scripting and linux.
Stackforce AI infers this person is a VLSI Design Engineer with a focus on ASIC development and physical design.
Location: Bengaluru, Karnataka, India
Experience: 2 yrs 2 mos
Skills
- Physical Design
- Power Optimization
Career Highlights
- Strong expertise in ASIC physical design flow.
- Proficient in static timing analysis and timing closure.
- Experienced in power optimization and integrity.
Work Experience
Mirafra Technologies
Physical Design Engineer I (9 mos)
Nanopowered
PDN Engineer (1 yr 5 mos)
RV-VLSI VLSI and Embedded Systems Design Center
ASIC Physical Design Engineer (6 mos)
Education
Bachelor of Engineering - BE at JSS Academy Of Technical Education Karnataka
Advanced Diploma in ASIC Design at RV-SKILLS Center For Emerging Technologies
