May 2025 – Jul 2025 · 2 mos · Guwahati, Assam, India · On-site

• Research Intern at Nanoelectronics and Semiconductor Devices Group – EnLightMe Group, Indian Institute of Technology (IIT) Guwahati
• Guided by: Dr. Arun Tej M, Associate Professor, Dept. of EEE
• Mentored by: Ms. Radharani Y., Ph.D. Scholar
• Research Area: Memristor Technology and ReRAM Crossbar Memory Architectures
• Worked on the design, fabrication, and characterization of memristor device based on perovskite material Cs3Bi2I9 for non-volatile memory and neuromorphic computing applications. The fabricated devices demonstrated bipolar resistive switching behavior with a high ON/OFF ratio of 6.4 × 10⁶, low set/reset voltages (1 V and –0.6 V), and operation under a 1 mA compliance current. The forming voltage was as low as –0.7 V, and the devices exhibited endurance beyond 10⁴ cycles, maintaining distinguishable binary states with Low Resistance State (LRS) in the kilo-ohm range and High Resistance State (HRS) above 90 MΩ.
• Despite the known retention limitations of perovskite materials (~10³–10⁴ seconds), we successfully enhanced retention to over 15 hours using Pavlovian conditioning techniques. This outcome suggests that with optimized fabrication protocols and controlled operational parameters, perovskite-based memristors could potentially rival oxide-based devices such as HfO₂ and TiO₂-based HP memristors.
• Simulated a non-linear memristor model in COMSOL Multiphysics, employing Pd electrodes and Tantalum Oxide, which exhibited classic pinched hysteresis I–V characteristics.
• Tried simulating a 4×4 ReRAM crossbar array in LAOSS Software, incorporating JV characteristics from the fabricated memristor to study sneak path current effects under AC conditions.
• Explored gating techniques and 1S-1R mechanisms using real device data to understand methods for sneak path suppression.
• Tried simulating theoretical memristor models — Linear, Non-Linear, Exponential, STBM, and TEAM in MATLAB, to analyze the IV Characteristics of the Models.

May 2024 – Jul 2024 · 2 mos · Bengaluru, Karnataka, India · On-site

• Research Intern at Sustainable Power Electronics Laboratory (SPELL), Indian Institute of Science (IISc), Bangalore.
• Research Area : Estimation and Optimization of Parasitic Inductance and Capacitance in SiC Power Converter PCB Layouts
• Guidance: Dr. Kaushik Basu, Associate Professor, Dept. of Electrical Engineering, IISc
• Mentorship: Dr. Manish Mandal, Ph.D. Scholar, SPELL Laboratory, Dept. of Electrical Engineering, IISc
• Accurate estimation and optimization of parasitic inductance and capacitance are critical in high-frequency SiC power converters, where even small parasitics can lead to increased switching losses, EMI issues, and reduced system efficiency.
• During my internship at the SPELL Laboratory, I focused on characterizing these parasitic effects in PCB layouts designed for SiC-based buck converters. Using ANSYS Electronics Desktop tools — Maxwell, Q3D Extractor, and HFSS — I performed detailed electromagnetic simulations to analyze how layout geometry and material properties influence parasitic behavior. I created graphical estimations across different dimensional configurations and dielectric constants to gain insights into parasitic trends. Based on this analysis, we optimized PCB layouts in KiCAD to reduce loop inductance and improve EMI performance. This work contributed to a research paper submitted to the IEEE Transactions on Power Electronics, aimed at advancing layout methodologies for reliable and efficient SiC-based power electronics.