Luca Amaru

CEO

Mountain View, California, United States14 yrs 11 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Leader in next-generation logic synthesis technologies.
  • Expert in electronic design automation and emerging technologies.
  • Proven track record in R&D leadership and innovation.
Stackforce AI infers this person is a leader in EDA with a focus on logic synthesis and optimization.

Contact

Skills

Core Skills

Logic SynthesisOptimization

Other Skills

Equivalence CheckingVLSI CADEDADigital IC DesignEmerging TechnologiesNanoelectronicsHardware ArchitectureComputer ArithmeticLow Power SystemsAlgorithmsData StructuresData Compression

About

Luca Amaru is Vice President of R&D within the Technology & Product Development Group at Synopsys Inc., based in Sunnyvale, CA. In this role, he leads the research and development of next-generation logic synthesis technologies, driving innovation at the forefront of electronic design automation. Dr. Amaru directs a global team of R&D engineers advancing the state of the art in logic synthesis.

Experience

14 yrs 11 mos
Total Experience
4 yrs 11 mos
Average Tenure
10 yrs 5 mos
Current Experience

Synopsys inc

7 roles

Vice President, R&D

Promoted

Jun 2026Present · 0 mo

Logic SynthesisOptimizationEquivalence CheckingVLSI CADEDADigital IC Design+8

Executive Director, R&D

Promoted

Sep 2024Jun 2026 · 1 yr 9 mos

Senior Director, R&D

Promoted

Feb 2024Sep 2024 · 7 mos

Principal R&D Engineer

Promoted

May 2022Feb 2024 · 1 yr 9 mos

Senior R&D Manager

Promoted

Jun 2019May 2022 · 2 yrs 11 mos

Staff R&D Engineer

Promoted

Jun 2018Jun 2019 · 1 yr

Senior II R&D Engineer

Jan 2016Jun 2018 · 2 yrs 5 mos

Stanford university

Visiting Researcher

Apr 2014Jul 2014 · 3 mos · San Francisco Bay Area, Stati Uniti

  • Logic synthesis for emerging technologies

Epfl

Doctoral Researcher

Sep 2011Dec 2015 · 4 yrs 3 mos · Lausanne Area, Svizzera

  • EDA for emerging technologies and applications - specialization in synthesis and optimization

Epfl - telecommunication circuits laboratory

VLSI Design Internship

Jun 2011Sep 2011 · 3 mos · Lausanne Area, Svizzera

  • ASIC design of a successive cancellation (SC) decoder for polar codes

Education

EPFL

Doctor of Philosophy (PhD)

Jan 2011Jan 2015

Alta Scuola Politecnica

Double degree excellence programme

Jan 2009Jan 2011

Politecnico di Milano

Master of Science - MS — Electronic Engineering

Jan 2009Jan 2011

Politecnico di Torino

Master of Science (M.Sc.) — Electronic Engineering

Jan 2009Jan 2011

Politecnico di Torino

Bachelor of Science (B.Sc.) — Electronic Engineering

Jan 2006Jan 2009

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