Nov 2021 – Present · 4 yrs 7 mos

• Working on convergence and PPA push for High Frequency ARM CPU and GPU cores and Synopsys IPs such as PCIe, DDR and UCIe using Synopsys implementation tools. Design: UCIe Responsibility: Lead team of 4 to perform PnR activities, performing total power reduction, Custom Clock building and routing to achieve high frequency. Performing custom placement to achieve high FMAX target. Performing all reliability checks and signo checks Instance Count: 6M Frequency: Read/Write at 32GHz Design: PCIe 6 Responsibility: Lead team of 4 to perform PnR activities, Design planning and validation of the budget that are generated for block level implementation and provided feedback to frontend design team regarding constraints that was provided. Top level integration. Worked on library pruning for cell selection to be used for optimization. Controlling threshold voltage group for last mile closure. Used guide bu er and balance points for structing better clock tree. Implemented transparent hierarchical optimization to reduce the TaT and ECO cycles. Instance Count: 6.5M Frequency: 2GHz,1GHz. Design: ARM CPUs Responsibility: Lead team of 4 to perform PnR activities, Design planning and validation of the budget that are generated for block level implementation. Banking of the cells to reduce area and power. Debanking to reduce bottle neck paths. Clock gating for reducing total power and controlling cloning of the clock gates to avoid bottle neck paths. Block level implementation, using attractions and bounds to control the placement of the design. H-tree Building, debugging H-tree to reduce skew between the tap points and reducing OCV impact on the clock tree. provided feedback to the customer with respect to floorplan. Density control and adding path margin for critical paths for optimizing the design better for timing convergence. Instance Count: 12M Frequency: 3.

Dec 2014 – Nov 2021 · 6 yrs 11 mos

• RTL to GDS was implemented with synthesizing the netlist and performing sanity checks over it. And then taking the netlist through the different physical design stages

Dec 2014 – Nov 2021 · 6 yrs 11 mos

• Design: Multiple Processors and Modem and test chips Responsibility: Lead team of 8 owning activity from synthesizing the RTL and performing sanity checks over it. And then taking the netlist through the di erent stages of physical design. Performed all signo to checks like logical and physical DRCs, timing fixes, reliability checks like IR drop and EM violations, LEC checks and cleaned physical DRCs.

Jun 2014 – Jan 2015 · 7 mos · India

Jun 2012 – Feb 2013 · 8 mos

• Responsibility: Helped in final closure of the projects by cleaning up the DRC and LVS and rolled couple of ECO’s.

May 2012 – Feb 2013 · 9 mos · Bangalore

• full chip floorplanning, power grid design, clock tree design, synthesis and timing optimization, place & route, timing closure, power/signal integrity analysis, to physical verification (DRC/LVS/Antenna).