Dhruv Shivhare

Software Engineer

Chennai, Tamil Nadu, India0 mo experience

Key Highlights

Expertise in ASIC backend implementation and physical design.
Proven track record in timing analysis and constraint setup.
Strong collaboration skills with verification teams.

Stackforce AI infers this person is a Semiconductor Design Engineer with a focus on ASIC physical design and timing analysis.

Contact

Skills

Core Skills

Physical DesignStatic Timing Analysis (sta)Asic Design Methodologies

Other Skills

ASIC backend implementationsynthesisfloorplanningplacementCTSroutingtiming analysisconstraint setupECO implementationRTL-to-GDSII flowverificationECOClock Tree SynthesisLogic SynthesisVerilog

About

A graduate of ITM Gwalior and Rajiv Gandhi Prodyogiki Vishwavidyalaya with a BTech in Electronics and Communications Engineering, currently a Junior VLSI Engineer at PRSsemicon Technologies. Skilled in ASIC backend implementation, with expertise in synthesis, floorplanning, placement, CTS, and routing for advanced chip designs using Cadence Genus and Innovus tools. At PRSsemicon Technologies, contributed to the Camera Serial Interface (CSI) project, focusing on timing analysis, constraint setup, and resolving violations alongside verification teams. Committed to delivering optimized and manufacturable designs, while fostering collaboration and leveraging technical skills for impactful semiconductor solutions.

Experience

0 mo

Total Experience

Average Tenure

Current Experience

Prssemicon technologies (a prsgroup company)

Junior VLSI Engineer

Jul 2025 – Present · 11 mos · Chennai, Tamil Nadu, India · On-site

Contributing to ASIC backend implementation as part of the Physical Design & STA team, working through the complete Synthesis-to-GDSII flow using Cadence Genus and Innovus tools.
Key Responsibilities & Achievements:
Implementing synthesis, floorplanning, placement, CTS, and routing for the Camera Serial Interface (CSI) project.
Designed and optimized a block with ~16K standard cell instances, achieving efficient area and power balance.
Focused on timing closure and post-route optimization, resolving setup and hold violations.
Collaborated with verification and signoff teams to ensure design functionality and manufacturability.
Developed strong command over timing analysis, constraint setup, and ECO implementation in backend design.
Tools & Technologies:
Cadence Genus | Cadence Innovus | STA | RTL-to-GDSII | Floorplanning | CTS | Routing | Timing Closure

ASIC backend implementationsynthesisfloorplanningplacementCTSrouting+5

coe for chip design | nielit noida

Apprentice

Feb 2025 – May 2025 · 3 mos · Noida, Uttar Pradesh, India · On-site

Learning the complete RTL-to-GDSII flow, including synthesis, floor planning, placement, routing, and signoff
Gaining hands-on experience with industry-standard EDA tools for physical design, timing analysis, and verification
Developing a strong understanding of ASIC design methodologies, semiconductor fabrication, and real-world chip development

RTL-to-GDSII flowsynthesisfloor planningplacementroutingverification+1