Guru Aarath Vuppuluri

Product Engineer

San Francisco, California, United States5 yrs 6 mos experience

Key Highlights

Expert in Static Timing Analysis and timing closure.
Proven track record in optimizing chip performance.
Strong collaboration with semiconductor design teams.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Static Timing Analysis and chip performance optimization.

Contact

Skills

Core Skills

Static Timing AnalysisTiming Closure

Other Skills

Synopsys PrimetimeDebuggingConstraints generationDesignSyncSynopsys toolsCadence SoftwareCadence TempusPlace & RouteInnovusPhysical DesignMicrosoft OfficeLeadershipVery-Large-Scale Integration (VLSI)Project ManagementC

About

As a Physical Design Engineer specializing in Static Timing Analysis (STA) at Tesla, I contribute to optimizing chip performance through advanced timing methodologies. Leveraging expertise in tools like PrimeTime and Tempus, I ensure design accuracy and reliability while addressing timing challenges effectively. With 7 years of experience in STA and timing signoff, I have developed a strong foundation in constraint generation, debugging, and power optimization across advanced nodes such as 3nm and 5nm. My focus is on supporting semiconductor design teams in achieving timing closure and enhancing performance metrics through collaborative efforts and innovative solutions.

Experience

5 yrs 6 mos

Total Experience

1 yr 4 mos

Average Tenure

Current Experience

Marvell technology

STA Engineer

May 2026 – Present · 1 mo · Santa Clara, CA · On-site

Tesla

Physical Design Engineer - STA

Nov 2025 – Apr 2026 · 5 mos · Palo Alto, CA · On-site

Cisco

Hardware Engineer

Nov 2024 – Jul 2025 · 8 mos · San Jose, CA · On-site

Create clock sheets for various operational modes, implementing necessary exceptions to optimize functionality and performance.
Generate chip top constraints and develop detailed constraints while debugging Synopsys Design Constraints (SDC) to identify and resolve potential issues and ensure accurate timing and performance metrics across the design.
Identify and address clock leak issues, SDC errors, and warnings to enhance design reliability.

Timing ClosureSynopsys PrimetimeStatic Timing AnalysisDebuggingConstraints generation

Nxp semiconductors

Design Engineer

Jul 2024 – Aug 2024 · 1 mo · Noida, Uttar Pradesh, India · On-site

Responsible for constraint generation and analysis for a partition working at 5nm, proactively identifying and debugging issues.
Collaborated closely with physical design teams to address critical path delays, contributing to achieving timing signoff.

Static Timing AnalysisTiming ClosureSynopsys PrimetimeConstraints generationDesignSync

Qualcomm

Engineer lll HMPD

Feb 2024 – May 2024 · 3 mos · Noida, Uttar Pradesh, India · On-site

Drove timing closure for two high-frequency 3nm blocks of Qualcomm’s snapdragon CPU, ensuring tapeout readiness.
Reduced leakage power by 5% through targeted power ECOs, optimising in multi-voltage designs.
Spearheaded automated ECO tools, reducing manual intervention and accelerating the design cycle.

Static Timing AnalysisTiming ClosureSynopsys PrimetimeSynopsys tools

Synopsys inc

Application Engineer Senior-1

Aug 2022 – Jan 2024 · 1 yr 5 mos · Noida, Uttar Pradesh, India

Resolved critical STA timing correlation issues across the full backend physical design flow for major semiconductor clients.
Delivered product enhancements as the CAE owner for the Auto-mux clock exclusivity feature, successfully implemented in the latest version.

Static Timing AnalysisTiming ClosureSynopsys tools

Cadence design systems

Application Engineer

Oct 2019 – Jul 2022 · 2 yrs 9 mos · Noida Area, India

Managed Tempus timing signoff solutions for top-tier automotive and processor chip designs, ensuring zero-critical violations at tapeout.
Analyse customer requirements and plan build release with Product Engineering and R&D team.
Awarded the Cadence Shine Award for driving a high-value Tempus contract renewal by enhancing client satisfaction.
Led the development and deployment of the IPD feature for a high-priority customer, ensuring alignment with project timelines and client requirements.
Collaborated with cross-functional teams to gather requirements, design solutions, and conduct thorough testing on customer designs.

Cadence SoftwareCadence TempusPlace & RouteInnovusStatic Timing AnalysisTiming Closure

Hcltech

Member Of Technical Staff

Aug 2018 – Aug 2019 · 1 yr · Noida Area, India · On-site

Interact with senior engineers to solve physical design problems.
Flow debugging
Provide feedback to RTL design team
Timing Signoff & ECO

Tekishub consulting services llc

Software Engineer- VLSI

Jun 2018 – Aug 2018 · 2 mos · Bangaon Area, India

Worked in HCL Technologies as third party employee and went through VLSI Physical Design training.

Intel corporation

Intern

Apr 2017 – Aug 2017 · 4 mos · Bangalore

Low Power VLSI Design
My responsibilities include:
Understanding the concept of UPF, choosing the right style which can consistently work through an entire flow
Having a broad-flow understanding of a full Low Power Methodology
Understanding how to run and test the various tools of a full Low Power Methodology