Devesh Deshpande — Product Engineer
Hi, I am Devesh Deshpande. I am passionate in VLSI. Presently working on Physical Design of DDR IP. I am interested for careers in Static Timing Analysis (STA) and Physical Design. I love to help people. I believe in collaboration. I want to change the world by making people's life simpler by my skills and learning. Work for a Cause, not for the Applause. - Gaur Gopal Das.
Stackforce AI infers this person is a VLSI Engineer with expertise in Physical Design and Static Timing Analysis.
Location: Nagpur, Maharashtra, India
Experience: 5 yrs 5 mos
Skills
- Static Timing Analysis
- Rtl Design
Career Highlights
- Experienced in Physical Design and Static Timing Analysis.
- Strong background in VLSI with major industry players.
- Passionate about collaboration and helping others.
Work Experience
Cadence
Physical Design Engineer 2 (1 yr 1 mo)
Synopsys Inc
Application Engineer I (1 yr 10 mos)
Intel Corporation
Physical Design Engineer (AXG Group) (10 mos)
NVIDIA
Hardware Intern (5 mos)
MeyvnSystems
RTL Design Intern (7 mos)
@ABHIVYAKTI
Event Management and Corporate Relations Head (1 yr 5 mos)
@TANTRAFIESTA
Event Management Co-Head (1 yr 8 mos)
Vishveshwarya National Institute of technology, NAGPUR
Research Intern (2 mos)
Education
Bachelor of Engineering - BE at Indian Institute of Information Technology, Nagpur
at New English High School & Junior College, Wardha, Maharashtra, India
School at Somalwar Academy Education Society
