Adithya Rithvikaran Karanam

Product Engineer

Bengaluru, Karnataka, India5 yrs 5 mos experience

Key Highlights

  • Expert in ASIC development lifecycle from RTL to verification.
  • Proficient in Verilog and SystemVerilog for robust design.
  • Strong collaboration skills across multidisciplinary teams.
Stackforce AI infers this person is a Semiconductor ASIC Design Engineer with expertise in RTL development and verification.

Contact

LinkedIn

Skills

Core Skills

Asic/ip Design & DevelopmentRtl Development

Other Skills

RTL codingCDC analysisLint checksDesign optimizationCross-functional collaborationLint verificationDesign architectureCross-functional coordinationLECSynthesisRTL modules designLintingVerdiRabbit RTL IntegrationLogic Synthesis

About

Experienced ASIC Design Engineer with a strong track record across the complete ASIC development lifecycle, from RTL design to verification and implementation. Proficient in RTL coding using Verilog and SystemVerilog, along with expertise in CDC analysis, Linting, synthesis, and Logical Equivalence Checking (LEC), ensuring robust and high-quality design delivery. Skilled in developing and optimizing digital designs and IP cores with a focus on performance, scalability, and reliability. Hands-on experience with leading industry tools, including Synopsys VCS, SpyGlass LINT, SpyGlass CDC, Questa CDC, Rabbit RTL Integration, Conformal LEC, and Design Compiler. With a solid foundation in digital communications, embedded systems, and signal processing, I bring a problem-solving mindset and attention to detail to every project. Known for effective cross-functional collaboration, I consistently contribute to delivering efficient, high-quality solutions aligned with project goals and timelines.

Experience

5 yrs 5 mos
Total Experience
1 yr 7 mos
Average Tenure
6 mos
Current Experience

Mettlesemi systems and technologies private limited

Senior Engineer – RTL Design

Dec 2025 – Present · 6 mos · Bengaluru · On-site

  • Executed end-to-end ASIC development lifecycle, including design specification, RTL coding, CDC analysis, and Lint checks.
  • Developed and optimized RTL designs, ensuring functionality, performance, and compliance with design standards.
  • Performed Clock Domain Crossing (CDC) analysis and Linting, identifying and resolving design issues to improve reliability and quality.
  • Collaborated with cross-functional teams across Design, Verification, and DFT, ensuring seamless project execution and delivery timelines.
  • Ensured design quality and compliance through systematic validation, debugging, and adherence to industry best practices.
  • Integrated multiple IP blocks into top-level RTL based on architectural specifications. Debugged functional issues arising from IP integration and supported debug activities.
RTL codingCDC analysisLint checksDesign optimizationCross-functional collaborationASIC/IP Design & Development+1

Quess corp limited

Senior Design Engineer

Dec 2024 – Jul 2025 · 7 mos · Bengaluru · On-site

  • Led key activities in the ASIC design flow, including RTL development, CDC analysis, and Lint verification.
  • Implemented and refined RTL architectures, ensuring design efficiency, scalability, and compliance with specifications.
  • Conducted design static checks (CDC, Lint) to identify issues early and improve overall design quality.
  • Coordinated with multidisciplinary teams to streamline development processes and achieve on-time project delivery
RTL developmentCDC analysisLint verificationDesign architectureCross-functional coordinationASIC/IP Design & Development+1

Insemi technology services pvt. ltd.

Senior Design Engineer

Jun 2024 – Oct 2024 · 4 mos · Bengaluru · On-site

  • Delivered ASIC design solutions across the full lifecycle, including RTL development (Verilog/SystemVerilog), LEC, CDC analysis, Lint checks, and Synthesis.
  • Ensured high-quality and reliable designs by following industry-standard methodologies and maintaining compliance with design protocols.
  • Enhanced design performance and efficiency through optimization techniques and continuous improvement of digital architectures
RTL developmentLECCDC analysisLint checksSynthesisASIC/IP Design & Development+1

Infoville solutions india private limited

Digital Design Engineer

Jun 2020 – Jun 2024 · 4 yrs · Bengaluru

  • Designed and enhanced RTL modules for IP-level ASIC frontend development, performing CDC analysis, Linting, and ensuring compliance with coding standards to improve design quality.
  • Executed Clock Domain Crossing (CDC) checks, resolved synchronization issues, and conducted Lint analysis to eliminate rule violations and ensure robust, error-free RTL design.
  • Supported Synthesis and Logic Equivalence Check (LEC), collaborating with cross-functional teams to ensure timely delivery of high-quality ASIC designs aligned with project specifications
RTL modules designCDC analysisLintingSynthesisLECASIC/IP Design & Development+1

Education

University of Leicester

Postgraduate Degree — Information and Communications Engineering

Sep 2018 – Sep 2019

SRM IST Chennai

Bachelor of Technology - BTech — Electronics and Communications Engineering

Jul 2013 – May 2017

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