B.A.Jaya Vardhan

DevOps Engineer

Andhra Pradesh, India3 yrs experience
Highly Stable

Key Highlights

  • Hands-on experience in ASIC design verification.
  • Proficient in developing verification environments for multiple IPs.
  • Strong foundation in RTL design methodologies.
Stackforce AI infers this person is a Semiconductor Design Verification Engineer with expertise in ASIC and RTL methodologies.

Contact

LinkedIn

Skills

Core Skills

Design VerificationAsic Design

Other Skills

RTL designverification environmentAPBEthernet IPUART IPSMBUS

Experience

3 yrs
Total Experience
3 yrs
Average Tenure
3 yrs
Current Experience

Synopsys inc

Contractor

Apr 2024 – Present · 2 yrs 2 mos · Hyderabad, Telangana, India · Remote

Moschip

Design Verification Engineer

Jun 2023 – Present · 3 yrs · Hyderabad, Telangana, India · On-site

  • Hands-on experience on: up-down counter(RTL design and verification environment), APB (Verification Environment), Ethernet IP (Verification Environment),UART IP (verification Environment), SMBUS (verification Environment)
RTL designverification environmentAPBEthernet IPUART IPSMBUS+2

Moschip institute of silicon systems (m-iss)

Trainee Engineer -Design Verification

Sep 2022 – Jun 2023 · 9 mos · Hyderabad, Telangana, India

  • Hands-on experience on: up-down counter(RTL design and verification environment), APB (Verification Environment), Ethernet IP (Verification Environment)
RTL designverification environmentAPBEthernet IPDesign VerificationASIC Design

Education

RAJIV GANDHI UNIVERSITY OF KNOWLEDGE TECHNOLOGIES, NUZVID

ece

Jan 2019 – Jan 2020

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