Yassmeen Derhalli — Product Manager
✅ PhD in formal verification of dynamic dependability analysis using HOL theorem proving. ✅ Experience in Datapath equivalence checking, SystemVerilog, SVA and UVM. ✅ Experience in digital circuits design flow and VHDL. ✅ Efficient problem solver, quick learner, self-driven and enthusiast to explore new domains.
Stackforce AI infers this person is a Hardware Verification Engineer with a strong focus on formal verification and digital design.
Experience: 17 yrs 6 mos
Skills
- Formal Verification
- Debugging
- Fpga Verification
- Digital Circuit Design
Career Highlights
- PhD in formal verification with expertise in theorem proving.
- Extensive experience in FPGA verification and digital circuit design.
- Strong problem-solving skills and a passion for learning.
Work Experience
Synopsys Inc
Senior Formal Verification Product Engineer (4 yrs 3 mos)
MDA
FPGA Verification Engineer (2 yrs)
Hardware Verification Group, Concordia University
Research Associate (2 mos)
Concordia University
Research Assistant (3 yrs)
Al Ahliyya Amman University
Lecturer (5 yrs 11 mos)
Lab Engineer (2 yrs 4 mos)
Education
Doctor of Philosophy - PhD at Concordia University
Master of Science - MS at New York Institute of Technology
Bachelor of Science - BS at Al Ahliyya Amman University
