David Jeyakumar S

Software Engineer

Tamil Nadu, India3 yrs 9 mos experience
Highly Stable

Key Highlights

  • Expert in ASIC RTL design and verification.
  • Proven track record in USB3.x HUB IP development.
  • Strong skills in RTL coding and debugging.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC development and RTL coding.

Contact

LinkedIn

Skills

Core Skills

Asic Rtl DesignRtl Coding

Other Skills

USB3.x HUB IPlintCDCRDCSynthesis

Experience

3 yrs 9 mos
Total Experience
3 yrs 4 mos
Average Tenure
5 mos
Current Experience

Wipro

Senior RTL Design Engineer

Jan 2026 – Present · 5 mos · Bengaluru, Karnataka, India · Hybrid

Smartdv technologies

ASIC RTL Design Engineer

Aug 2022 – Dec 2025 · 3 yrs 4 mos · Bengaluru, Karnataka, India · On-site

  • Took ownership on USB3.x HUB IP,worked on various features updation and development of dual lane support,lint,CDC,RDC, Synthesis
USB3.x HUB IPlintCDCRDCSynthesisASIC RTL Design+1

Education

Government College of Engineering, Tirunelveli

BE - Bachelor of Engineering — Electronics and Communication Engineering

Jan 2016 – Jan 2019

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