Sep 2024 – Aug 2025 · 11 mos · Munich, Bavaria, Germany · On-site

Jan 2024 – Sep 2024 · 8 mos · On-site

• Project: Work with Samsung Foundry team
• Leading team for new tool feature enablement and existing project support for tool issues. .
•  SPICE-PT correlation for SF2 certification, Vmin/SMVA related issues have been handled.
•  Primeclosure deployment for 2nm {SF2} , Closely Working with SOC team for design closure.
•  3DIC features deployment for timing signoff. Project: Worked with Samsung Foundry team on pessimism reduction and ML based corner reduction.
•  SMC enablement to reduce no of corners to run. Attribute based CTPM {Compact timing and power model} enablement {follow up with RnD and closure with client} were part of new feature testing and deployment.
•  Leading and guiding juniors for multiple PT/PS/PC issues.
• Skills: Reasoning Skills · EDA · Primetime · Timing Closure · ECO. PnR . Voltage · Scripting · Timing · Power Consumption · Communication · Written Communication · Problem Solving · Analytical Skills

Feb 2022 – Feb 2024 · 2 yrs · On-site

• Project: Work with Samsung Foundry team
• Responsible for new tool feature enablement and existing project support for
• tool issues.
•  SMC enablement, Attribute based CTPM enablement {follow up with
• RnD and closure with client} were part of new feature testing and
• deployment.
•  SPICE-PT correlation for 4LPP certification, Vmin/SMVA related issues
• have been handled.
•  Primeclosure deployment for 3nm/4lpe, Closely Working with SOC team
• for design closure.
•  3DIC features deployment for timing signoff.

Dec 2019 – Mar 2022 · 2 yrs 3 mos · On-site

• 👉Staff Engineer
• Qualcomm Technologies, Noida, Uttar Pradesh
• Project: STA Methodologies and support
• Was Responsible for 3 broad activities:
•  Tech node enhancements: working with vendors {Synopsys and cadence to
• use latest technologies like hierarchical STA, PGV to implement in QC env}.
• Lastly Worked on 4nm enablement.
•  Custom request for all “test mode teams” across Qualcomm.
• Enhancements related to CB-DFT, test timing closure, clock offset flow.
•  Support on the existing flow and mentoring couple of resources to pick up
• pace and helping in resolving critical tickets.

Jul 2016 – Dec 2019 · 3 yrs 5 mos · On-site

• 👉Senior Tech Lead (Jul,2016-Dec2019):
• Project: QOR improvement from 14-5nm tech nodes for automotive and 5G
• mobile chips.
•  Responsible for improving digital physical design activities for 5G modem
• products. Over the year engaged related to simulating tightened corners
• on a per layer basis.
•  Direction provided for the implementation and timing sign-off activities of
• an entire SOC in 14lpp.
•  Implementation and timing sign-off activities for 14lpp, Responsible for the
• support of implementation of most of the blocks. This includes: · Closely
• worked with designers to come up on working strategy for STA flow
• enhancement, to improve QOR.
•  Guided the CTS implementation for user to choose from multiple input
• settings with Pro/Cons of all settings to be use Design has more than 100
• clocks with frequencies 2.5 GHz, 1.25 GHz,625 MHz, 312.5 MHz · CTS
• implementation activities to make timing sign-off easier at high frequencies.
•  PnR flow setup & QOR improvement. · As a part of joint development effort
• b/w Synopsys and Qualcomm, handled multiple 7-ff issues.

Jan 2015 – Jun 2016 · 1 yr 5 mos · Noida Area, India · On-site

• Block Level PnR and Timing closure {28lpu-BT chip}:
•  Tape out of 3 blocks with Frequency 1.2 GHz and 800 MHz with complexity
• 780K, 738K and 1.03M gates
•  Constraints Development, Placement, Clock tree synthesis, Routing and STA.
•  Re-synthesis of 6 blocks because of new feature addition in design.
•  Timing closure involved so many manual modifications including manual
• routing, flop, and logic duplication, splitting of multibit flop and flop/logic
• movements.

May 2011 – Dec 2014 · 3 yrs 7 mos · Pune Area, India · On-site

•  Worked on Different clients for tech nodes like 45nm/14nm/28nm.
•  Did Synthesis using DC for wireless com chip {Block level}.
•  Responsible for block level floor plan, Place and route, signoff checks.
•  Timing closure in PnR/ECO flow.
•  Responsible for Physical Implementation and STA for 2 partitions – PCIe and
• SATA for SoC at 28nm technology node.
•  Along with block implementation, I also helped Senior Engineers in Top Level
• DRC/LVS issues.
•  Wrote useful TCL utilities to automate the P&R flow Programming.
•  Mentored team of new joiners for almost a year

May 2010 – May 2011 · 1 yr · Haridwar, Uttarakhand, India · On-site

•  Quality assurance Engineer for the devices.
•  Also, worked with sales team to boost up the business.