Jinwoo Lee — Product Engineer
foundation ip design -Develop and optimize standard cell layouts (combinational and sequential/flip-flop) across advanced technology nodes including Samsung 2nm and TSMC 2nm. -Focus on area, performance, and reliability optimization, achieving the best PPA (Power, Performance, Area) balance. -Perform comprehensive cell verification including DRC, LVS, Pin Access, RGPA, EM, and duality checks. -Analyze trade-offs implement placement and routing for optimal cell architecture. -Deliver high-quality cell libraries meeting stringent design and verification requirements. Skilled in Synopsys Custom Compiler and Synopsys ICV. ------------------------------------------------------------------------------------------------------------------ Experience & Understanding Physical design -Strong understanding of entire physical design flow, from floorplan to GDS-out. -PPA Push using DSO.ai with Fusion Compiler
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in physical design and EDA tools.
Location: Gyeonggi, South Korea
Experience: 4 yrs 9 mos
Skills
- Physical Design
- Eda(전자설계자동화)
Career Highlights
- Expert in standard cell layout design for advanced technology nodes.
- Achieved optimal PPA balance in cell library development.
- Strong understanding of the entire physical design flow.
Work Experience
Synopsys Inc
R&D Sr Engineer (1 yr)
R&D Engineer (2 yrs 7 mos)
ASIC/SOC
ASIC Physical Design Engineer (1 yr 2 mos)
Education
학사 at Hanyang University
