Promit Mandal

Product Engineer

New Delhi, Delhi, India5 yrs experience

Key Highlights

  • Experienced in RTL design and VLSI projects.
  • Led IoT-based EV detection system development.
  • Strong foundation in digital electronics and circuit design.
Stackforce AI infers this person is a VLSI and IoT specialist with a focus on digital design.

Contact

Skills

Core Skills

Rtl DesignVlsi And Digital System DesignInternet Of Things (iot)Analog And Digital Electronics

Other Skills

Synthesisclocking constrainsSTAfusion compilerFormalitySynopsys FormalityVC SpyglassScriptingVerilogSpyglassSYNOPSYS VCS TOOLDigital system designPCIeEthernetLogic Synthesis

About

πŸ‘‹ Hello, I'm Promit Mandal, ASIC Digital Design Engineer at Synopsys, where I am a part of Test Chip Design team, working in interfacing IP, crafting RTL codes in Verilog, and using tools like Synopsys VCS for simulation purposes, Verdi, DC Compiler and SPYGLASS for linting. πŸŽ“ I hold a degree in Electrical Engineering from Delhi Technological University, where I was actively engaged in extracurriculars such as NSS DTU and IEEE DTU, and proudly served as the Class Representative for my batch. πŸ”‘ Key Skills: RTL Design Computer Architecture VLSI and Digital System Design Verilog Analog and Digital Electronics Proficient in Circuit Designing Software I'm passionate about pushing the boundaries of digital design and contributing to groundbreaking projects. Let's connect and explore opportunities to collaborate

Experience

5 yrs
Total Experience
1 yr 11 mos
Average Tenure
1 yr 11 mos
Current Experience

Synopsys inc

3 roles

ASIC Digital Design Sr Engineer

Promoted

May 2026 – Present Β· 1 mo Β· Noida, Uttar Pradesh, India

Synthesisclocking constrainsSTAfusion compilerFormalitySynopsys Formality+4

ASIC Digital Design Engineer

Jul 2024 – May 2026 Β· 1 yr 10 mos Β· Noida, Uttar Pradesh, India

VerilogSpyglassSYNOPSYS VCS TOOLDigital system designPCIeEthernet+7

ASIC Digital Design Intern

Jan 2024 – Jun 2024 Β· 5 mos Β· Noida, Uttar Pradesh, India

National service scheme, dtu

3 roles

General Secretary

Jun 2023 – Apr 2024 Β· 10 mos

Executive

Jul 2022 – Jun 2023 Β· 11 mos

Member

Dec 2021 – Jul 2022 Β· 7 mos

Delhi technological university (formerly dce)

Digital Design Research Intern

Jun 2023 – Aug 2023 Β· 2 mos Β· Delhi, India

  • Designed Radiation Hardened Double Node Upset Latch in 90nm and 45nm CMOS Technology.

Defence research and development organisation (drdo)

VLSI INTERN

Jun 2022 – Jul 2022 Β· 1 mo Β· Delhi, India

  • Research Project: LOW POWER VLSI DESIGN
  • did analysis of adiabatic circuits and methodologies used in CMOS Technology for power optimization.
Cadence VirtuosoMOS-VLSIDigital ElectronicsDigital system designVLSI and Digital System DesignRTL Design

Selectricgo ev solution pvt. ltd.

3 roles

Technical Team Member

May 2022 – Jan 2023 Β· 8 mos Β· Delhi, India Β· On-site

Hardware Team Lead

Feb 2022 – Jun 2024 Β· 2 yrs 4 mos Β· Delhi, India Β· On-site

  • built the IOT protocol based electronic system setup for EV detection at charging station.
ESP32 MicrocontrollersArduino IDEPrinted Circuit Board (PCB) DesignInternet of Things (IoT)Transmitter Systems DesignUniversal Asynchronous Receiver/Transmitter (UART)+1

Project Intern

Feb 2022 – Apr 2022 Β· 2 mos Β· Delhi, India Β· On-site

Ieee dtu

Member

Nov 2021 – Apr 2024 Β· 2 yrs 5 mos Β· Delhi, India

Desh ke mentor

2 roles

Student cordinator

Oct 2021 – Mar 2024 Β· 2 yrs 5 mos Β· Delhi, India

Member

May 2021 – Oct 2023 Β· 2 yrs 5 mos Β· Delhi, India

Education

Delhi Technological University (Formerly DCE)

Bachelor of Technology - BTech β€” Electrical engineering

Sep 2020 – May 2024

Lovely Public Sr. Sec. School

Science β€” Class 12th

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