Aug 2020 – Jan 2024 · 3 yrs 5 mos · Bengaluru, Karnataka, India

• Building wireless chips, power domain chips by contributing in the front end ASIC Design cycle from RTL to netlist and supporting backend and systems teams
• ◦ 5G ORAN based 8T8R Wireless chip:
• ∗ Designed Half-band 2x4 interpolation and 2x1 decimation filters with bypass functionality for four sample rates
• ∗ Designed VSWR capture module for Tx and FB samples and memory controller module for captured samples
• ∗ Designed the test mux, interrupt, register, clock and reset modules for the feedback datapath clock hierarchy
• ∗ Designed smaller design hooks at the sub-system hierarchical level like delay blocks and integrated various IPs
• ∗ Developed the SDC constraints for top level as well as block level modules following the clocking architecture
• ◦ Power sequencer chip that drives four dedicated Point-of-Load power converters through DVS:
• ∗ Designed, modified and reused existing I2C IP by understanding it to meet register and OTP requirements
• ∗ Designed the register top and the register modules in core clock domain as per the register map put in uarch
• ∗ Owned and debugged the complete design consisting of Power, DAC, OTP FSMs and ensured bug free RTL
• ∗ Run lint, CDC checks, Code-coverage, delivered FPGA bit map and executed Post-silicon validation test cases
• ◦ Point-of-Load Power Mgmt. IC with PMBus/SVI3 Interface for high precision telemetry and DVS:
• ∗ Delivered the V3 tape-out goals through RTL design verification support and debugging simulations
• ∗ Modified the test cases according to V2 and V3 RTL design changes in both SV and UVM environments
• ∗ Executed Code-coverage by merging the regression results to ensure RTL validation for the existing test plan
• ∗ Familiarized with the PMBus and SVI3 Interface protocols’ specifications and the pinout of the chip top

Jul 2019 – Jul 2020 · 1 yr · Delhi, India

Sep 2017 – Jul 2018 · 10 mos · Bina, Madhya Pradesh, India

• Worked on analytical systems from OEMs like GE Sensing, Ametek, ABB, Thermo Scientific, etc.
• Worked on control loops in DCS and interlocks in PLC to reduce downtime and ensure safe operations

Sep 2016 – Aug 2017 · 11 mos · Bina, Madhya Pradesh, India

Jul 2015 – Dec 2015 · 5 mos · Bengaluru Area, India

• Product verification, unit verification of PCIe
• Automation of controller design, integration of new RTL
• Link up verification, timing and bandwidth requirements

May 2014 – Jul 2014 · 2 mos · Singrauli, Madhya Pradesh, India