Deepika Pathak — Product Engineer
Experienced VLSI & Embedded Systems professional with an MTech, currently ensuring quality and performance in Synopsys's Fusion Compiler Tool. Specializing in Static Timing Analysis (STA) product validation, I address customer RTL to GDSII timing issues and enhance tool quality by analyzing and resolving issues. Skilled in monitoring version changes and ensuring robust QoR, I bring strong analytical, communication, and detail-oriented capabilities. Passionate about physical design and committed to operational excellence, I thrive in collaborative environments. Let's connect to explore technical synergies and drive innovation together.
Stackforce AI infers this person is a VLSI and Embedded Systems expert with a focus on tool validation and performance.
Location: Noida, Uttar Pradesh, India
Experience: 3 yrs 10 mos
Skills
- Fusion Compiler
- Synopsys Ic Compiler
- Static Timing Analysis
- Rtl Design
Career Highlights
- Expert in Static Timing Analysis and tool validation.
- Strong analytical and communication skills.
- Passionate about physical design and operational excellence.
Work Experience
Synopsys Inc
Application Engineering, Sr Engineer (2 yrs 4 mos)
Cadence Design Systems
STA Engineer (1 yr 6 mos)
VTOL Aviation India Private Limited
Radio Frequency Engineer (1 yr 3 mos)
Indian Oil Corp Limited
Summer Intern (1 mo)
Education
Master of Technology - MTech at ABV- Indian Institute of Information Technology and Management, Gwalior, India
B.Tech at BABU BANARASI DAS INSTITUTE OF TECHNOLOGY AND MANAGEMENT
CLASS XII at Silver Bells senior secondary school, Gwalior,M.P.
CLASS X at Invalid27070908
