Arthur Nigoyan

Software Engineer

12 yrs 5 mos experience

Highly Stable

Key Highlights

Expert in SoC design integration and EDA automation.
Proven track record in scalable automation architecture.
Strong collaboration skills across cross-functional teams.

Stackforce AI infers this person is a Semiconductor Engineering expert specializing in EDA Automation and SoC Design Integration.

Contact

Skills

Core Skills

Soc Design IntegrationEda Automation

Other Skills

automated RTL integrationarchitecture for Memory/Hierarchical systemsautomationdebugginginfrastructure improvementsautomation toolsmemory systemshierarchical systemsflow efficiencyscriptingvalidation infrastructureconfiguration generationSoC integrationdata convertersGDS verification

About

Senior Staff Engineer with 12 years of experience in ASIC design, SoC integration, and EDA automation. Expert in automation architecture, data conversion tools (PDL, ICL, CTL), regression infrastructure, and GDS verification. Proven track record in leading the architecture for memory and hierarchical systems, improving engineering productivity through scalable automation, and collaborating across cross-functional teams to solve complex integration challenges.

Experience

12 yrs 5 mos

Total Experience

12 yrs 5 mos

Average Tenure

12 yrs 5 mos

Current Experience

Synopsys inc

8 roles

Senior Staff Engineer

Promoted

May 2026 – Present · 1 mo

Developing scalable SoC design integration solutions utilizing automated RTL integration
methodologies.
Directing the architecture and automation for Memory/Hierarchical systems generation, integration, and validation.
Collaborating with cross-functional engineering teams to provide automation, debugging, and infrastructure improvements.

SoC design integrationautomated RTL integrationarchitecture for Memory/Hierarchical systemsautomationdebugginginfrastructure improvements+2

Staff Engineer

Feb 2024 – May 2026 · 2 yrs 3 mos

Developed and verified automation tools for the generation, integration, and validation of memory and hierarchical systems across sub-chip and SoC designs, including support for external pipelines.
Improved flow efficiency and reliability through the architecture of scalable scripting and validation infrastructure.

automation toolsmemory systemshierarchical systemsflow efficiencyscriptingvalidation infrastructure+2

Software Engineer SR I

Promoted

Mar 2021 – Feb 2024 · 2 yrs 11 mos

Developed automation tools for the automatic configuration generation and SoC integration of Memory/Hierarchical systems.
Created data converters and automation utilities for multiple formats including PDL, ICL, CTL,
and LVLIB.
Built tool for pattern extraction from ICL/PDL (IEEE 1687, IEEE 1500, IEEE 1149, IEEE 1838).
Developed scripts for GDS verification flows, bitmap generation, and strap extraction.

automation toolsconfiguration generationSoC integrationdata convertersGDS verificationbitmap generation+3

R&D Engineer, Sr I

Promoted

Oct 2020 – Mar 2021 · 5 mos

Contributed to semiconductor R&D projects with a focus on design verification and automation.
Supported activities related to tool development, validation, and infrastructure enhancement.

design verificationautomationtool developmentvalidationinfrastructure enhancement

ASIC Digital Design Engr, Sr I

Sep 2020 – Oct 2020 · 1 mo

ASIC Digital design engineer II

Promoted

Jun 2017 – Sep 2020 · 3 yrs 3 mos

Developed data converters for PDL, ICL, and CTL formats.
Created and refined automation tools for pattern extraction and view translation.
Designed scripts for GDS verification, bitmap generation, and strap extraction.
Participated in the development and verification of virtual memory and IP compilers.
Managed regression testing, debugging, and the optimization of test coverage.

data convertersautomation toolspattern extractionview translationGDS verificationbitmap generation+2

ASIC Digital design engineer I

Nov 2014 – Jun 2017 · 2 yrs 7 mos

Contributed to the development and verification of virtual memory and IP compilers.
Supported ASIC design verification and various automation activities.

virtual memoryIP compilersASIC design verificationautomation activities