Subhanjan Konwer

Software Engineer

Austin, Texas, United States3 yrs 2 mos experience

Key Highlights

Expertise in RTL design for high-performance CPUs.
Contributed to Snapdragon X Elite CPU development.
Developed automation scripts for memory integration.

Stackforce AI infers this person is a Semiconductor Engineering Specialist focused on RTL design and performance optimization.

Contact

Skills

Core Skills

Rtl Design

Other Skills

Python (Programming Language)Computer EngineeringC (Programming Language)Clock Domain Crossing DesignConformal Low Power ChecksLinuxLow-power DesignLint ChecksVery-Large-Scale Integration (VLSI)VerilogEngineeringMachine LearningShell ScriptingTcshProblem Solving

About

I’m a hardware engineer focused on high-performance and efficient compute design. Previously, I worked at Qualcomm on the Snapdragon X Elite 2, their highest-end CPU, contributing to RTL design. I’m now interning at NVIDIA in the GPU Performance Monitoring Unit, where I design RTL for performance monitoring logic. I’m drawn to the details that drive real-world performance, from architecture and microarchitecture to PPA and silicon efficiency. Let’s connect if you’re into chips, architecture, or performance engineering.

Experience

3 yrs 2 mos

Total Experience

1 yr 6 mos

Average Tenure

2 mos

Current Experience

Nvidia

2 roles

RTL Design

Apr 2026 – Present · 2 mos · Austin, TX · On-site

GPU performance monitoring unit.

ASIC Design Intern

Jun 2025 – Sep 2025 · 3 mos · Austin, TX · Hybrid

Developed architectural alternatives for the GPU PMU to enhance monitoring bandwidth and fairness across threads.
Investigated PMU microarchitectures to maximize bandwidth utilization per cycle across diverse GPU workloads.
Analyzed thread-level fairness mechanisms to ensure equitable resource distribution in multi-threaded monitoring scenarios.

RTL DesignPython (Programming Language)

Uc san diego

Student Researcher

Mar 2025 – Dec 2025 · 9 mos · San Diego, California, United States · On-site

Vertically-Integrated VLSI Information Processing (VVIP) Lab:
Building hardware accelerators for ML-applications.

Qualcomm

4 roles

Engineer

Promoted

Dec 2023 – Aug 2024 · 8 mos · Noida, Uttar Pradesh, India

Worked on CPU Subsystem for the next-generation (Snapdragon X-elite) compute-chip based on Nuvia CPUs.

RTL DesignComputer Engineering

Associate Engineer

May 2022 – Dec 2023 · 1 yr 7 mos · Noida, Uttar Pradesh, India

Worked on CPUSS based on ARM v9 (Kryo) architecture for Snapdragon 4 Gen2 (a project under #5GForAll)
Achievements + Highlights
Analyzed and updated CPU sequence facilitated by logic addition for faster core- PLL bring up post Low Power Mode (LPM) exit, thereby improving CPU wakeup time from idle state.
Integrated RISC-V-based CPU co-processor in CPUSS for Dynamic Clock and Voltage Scaling (DCVS) and power states management. Subsequently made firmware edits for enhancing CPU performance in turbo mode.
Identified and rectified a potential CDC issue that had been carried on in CPUSS designs as legacy.
Worked on setting up, analyzing, and closing on PLDRC, CDC, CLP and Synth-elaboration issues on CPUSS for quality design.

RTL DesignC (Programming Language)

Interim Engineering Intern

Jan 2022 – May 2022 · 4 mos · Noida, Uttar Pradesh, India

I have worked on analyzing/editing RTLs and closing on PLDRC and CDC issues.

Clock Domain Crossing DesignConformal Low Power Checks

Summer Intern

May 2021 – Jul 2021 · 2 mos · India · Remote

Developed a script for automating the integration of Qualcomm’s in-house memories in ARM cores.
Key Challenges
The memory configuration - the address bus width, memory length and data width – were at times different between the requirements and the available memories, so the script had to decide on the number of such memory instances accordingly, take care of extra logic (d-bit splitting and memory access arbitration) and ensuring proper connectivity.

Python (Programming Language)Linux