Chaitanya Gaikwad — Software Engineer

As a dedicated ASIC Physical Design Engineer with over 7+ years of experience, I specialize in working on complex designs across advanced technology nodes, including 3nm, 7nm, 16nm, and 28nm. My expertise spans handling multi-million gate count blocks and subsystems such as DDR, PCIe, and NAND, all the way through to block-level signoff and worked on 2+ tapeouts. I have a strong foundation in the complete ASIC design flow, from RTL to GDSII, with hands-on experience in Physical Verification (DRC, LVS, Antenna) and Block-Level Static Timing Analysis (STA). I am well-versed in industry-leading EDA tools, including Synopsys Fusion Compiler, ICC, ICC-II, PrimeTime, IC Validator, and StarRC, ensuring top-tier design optimization and validation. With a solid understanding of CMOS and VLSI fundamentals, I bring strong analytical, design, and problem-solving skills to every project. I also have practical programming experience in Tcl, Shell scripting, and Makefile, enabling me to streamline workflows and automate processes efficiently. My passion lies in delivering high-performance, scalable designs while continually learning and adapting to the ever-evolving landscape of ASIC design.

Stackforce AI infers this person is a highly skilled ASIC Physical Design Engineer specializing in VLSI and semiconductor design.

Location: Bengaluru, Karnataka, India

Experience: 7 yrs 4 mos