Jaffar Ahmed

Product Manager

Bengaluru, Karnataka, India13 yrs 10 mos experience

Highly StableAI Enabled

Key Highlights

Filed combined patent on FPGA synthesis validation methodology.
Nominated for ACE2022 and ACE2023 awards for quality and innovation.
Led validation for multiple FPGA customers.

Stackforce AI infers this person is a highly skilled EDA professional with expertise in FPGA synthesis and validation methodologies.

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Skills

Core Skills

Logic SynthesisFunctional VerificationHdl Designer

Other Skills

VCSSynplify ProVerdiArtificial Intelligence (AI)MATLABSimulinkShell ScriptingXilinx VivadoPerlPython (Programming Language)Algorithmic Trading

About

Filed combined patent on FPGA synthesis validation methodology using machine generative models and drive team to execute validation of Synthesis tool for multiple FPGA customers. Models are developed and deployed across validation of memory inference flow, other areas on OEM FPGAs such as logic synthesis and DSP. I enjoy the work with highly enthusiastic team, seeking to learn and innovate techniques to develop new solutions for improving reliability of products for customer satisfaction. Professional experience: 3 years R&D engineer: Matlab Simulink HLS IP development 11+ years of engineering and management experience in the Synopsys India on EDA tool validation.

Experience

13 yrs 10 mos

Total Experience

4 yrs 11 mos

Average Tenure

4 yrs

Current Experience

Synopsys india pvt ltd

Applications Engineering Manager

Jun 2022 – Present · 4 yrs · Bangalore Urban, Karnataka, India · On-site

Managing Synplify release portfolio for 5 different FPGA vendors and assisting team for all vendor Synplify mainstream release validation.

Logic SynthesisFunctional VerificationVCSSynplify Pro

Synopsys

Corporate applications engineer

Jan 2015 – May 2022 · 7 yrs 4 mos · Bengaluru, Karnataka, India · On-site

Worked on validation of Synplify releases for individual FPGA customers such as Achronix, Pango.
Invented and patented novel technique on Verification methodology using machine generative models.
o Highly reliable and acknowledged by industry leaders for improved quality in terms of crashes, preventing functional issues (logical simulation failure after synthesis).
o Nominated for ACE2022, ACE2023 company wide prestigious award for Quality and innovation.
Holding good experience in debugging simulation using VCS/Verdi or any other simulators.

Logic SynthesisFunctional VerificationVCSVerdi

Synopsys ind pvt ltd

Research And Development Engineer

Jul 2012 – Jan 2015 · 2 yrs 6 mos · Bengaluru, Karnataka, India

Worked on development of mathematical blockset in SMC compiler which is integrated into Simulink HDL library for HLS synthesis.
Key areas of IP development includes Digital direct Frequency synthesis (DDS), single channel , multichannel IP, multivariate FIR filters, floating point arithmetic blocks etc.
Achieved certificate of appreciation from Group Director for contribution on DDS blockset.

HDL DesignerMATLABSimulink