Chaoqun Wei

CTO

San Francisco, California, United States13 yrs 9 mos experience

Highly Stable

Key Highlights

Expert in ASIC digital design and CPU architecture.
Led multiple advanced semiconductor projects.
Strong background in RISC-V architecture development.

Stackforce AI infers this person is a semiconductor design expert with a focus on CPU architecture and ASIC development.

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Skills

Core Skills

Application-specific Integrated Circuits (asic)Cpu DesignMicroarchitecture

Other Skills

RTL DevelopmentComputer ArchitectureDebuggingTiming ClosureRTL DesignLogic DesignVerilogTCLModelSimCadenceUnixSynopsys toolsLintDesign SpecificationsSpyglass

About

Highly motivated and innovative ASIC digital design engineer. Experienced in computer architecture, digital circuit, and vector DSP processor. Passionate about discovery and development advanced architecture and micro architecture to provide state of the art products. Enthusiastic team player adept at providing leadership while also learning from fellow team members.

Experience

13 yrs 9 mos

Total Experience

7 yrs 4 mos

Average Tenure

0 mo

Current Experience

Globalfoundries

PMTS ASIC Digital Design

Jun 2026 – Present · 0 mo · Santa clara · On-site

Synopsys processor IP team merged with MIPS under GlobalFoundries
Continue on RISC-V CPU projects

Application-Specific Integrated Circuits (ASIC)RTL DevelopmentCPU designComputer ArchitectureDebuggingMicroarchitecture+9

Synopsys inc

2 roles

CPU micro-architect, principal ASIC digital design

Jun 2014 – Jun 2026 · 12 yrs · Mountain View

Synopsys Processor IP solution
Tech lead of:
Private L2 Cache (L2C)
Configurable cache size and number of slices
Advanced PLRU
MOESI
L1 cache VIPT aliasing mechanism
Prefetch
Bus protocol
ECC
Memory management unit (MMU)
SV32/SV39/SV48
ITLB/DTLB/L2 TLB
Hardware-based page table walker (PTW)
Translation cache to speedup page table walk
Risc-V hypervisor extension - two stage address translation (nested paging)
ECC
Risc-V advanced interrupt architecture (AIA)
Fused core-level interrupt controller(CLINT) and incoming MSI controller(IMSIC)
Interrupt fast delivery mode up to 2304 external interrupts
Programmable priorities arbitration, nested preemptive
Interrupt virtualization
Inter-processor interrupt (IPI)
ARC Vector Processor (VPX)
VLIW isa, SIMD architecture
Vector pipeline: instruction align, decode, dispatch, scoreboard, dependency/forwarding
Vector arithmetic: ALU, multiplier, etc.
Vector register file, guard register file, predicate register file