Kaushal K.

Software Engineer

Kanpur, Uttar Pradesh, India2 yrs 4 mos experience
Highly Stable

Key Highlights

  • Expert in Static Timing Analysis and Signoff processes.
  • Strong foundation in VLSI design and embedded systems.
  • Hands-on experience with leading EDA tools at Synopsys and Intel.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in Static Timing Analysis and EDA tools.

Contact

LinkedIn

Skills

Core Skills

Static Timing AnalysisSignoff

Other Skills

Synopsys PrimetimeConformal LECFusion compilerTweakerPrimeECOStarRCDebuggingRTL DesignLayout Versus Schematic (LVS)Application-Specific Integrated Circuits (ASIC)AnalogCMOSComputer-Aided Design (CAD)Problem SolvingIntegrated Circuits (IC)

Experience

2 yrs 4 mos
Total Experience
2 yrs 4 mos
Average Tenure
2 yrs 4 mos
Current Experience

Synopsys inc

3 roles

Senior Application Engineer

Promoted

Feb 2024 – Present · 2 yrs 4 mos

Static Timing AnalysisSynopsys Primetime

Application Engineer II

Jan 2024 – Feb 2024 · 1 mo

Static Timing AnalysisSignoff

Intern (Technical - Engineering)

Aug 2023 – Dec 2023 · 4 mos

Static Timing AnalysisSynopsys Primetime

Intel corporation

Graduate Technical Intern

Jul 2022 – Jun 2023 · 11 mos

Conformal LECFusion compiler

Education

Maulana Azad National Institute of Technology

M.TECH • VLSI DESIGN & EMBEDDED SYSTEMS

Jan 2021 – Jan 2023

Madan Mohan Malaviya University of Technology

B.tech

Jan 2016 – Jan 2020

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