Davit Astvatsatryan

Software Engineer

Yerevan, Yerevan, Armenia11 yrs 5 mos experience
Highly Stable

Key Highlights

  • Over 10 years of experience in ASIC physical design.
  • Expertise in Static Timing Analysis and SRAM memory compilation.
  • Proficient in Python and automation for circuit design.
Stackforce AI infers this person is a Semiconductor Engineering expert with a focus on ASIC design and timing analysis.

Contact

Skills

Core Skills

Static Timing Analysis

Other Skills

PrimetimeCircuit DesignAutomationPython (Programming Language)Computer SimulationsScriptingProblem SolvingSRAMDynamic Random-Access Memory (DRAM)CommunicationData StructuresAlgorithmsLinuxSQLGit

About

SRAM memory compiler and Static Timing Analysis engineer at Synopsys Inc. with over 10 years of job experience.

Experience

11 yrs 5 mos
Total Experience
10 yrs 3 mos
Average Tenure
1 yr 2 mos
Current Experience

Cisco

Senior ASIC Physical Design Engineer

Apr 2025Present · 1 yr 2 mos · Yerevan, Armenia · On-site

Synopsys inc

4 roles

Senior Supervisor, Static Timing Analysis

Jan 2024Apr 2025 · 1 yr 3 mos

Senior Static Timing Analysis Engineer

Promoted

Sep 2021Jan 2024 · 2 yrs 4 mos

Static Timing AnalysisPrimetime

SRAM Memory Compiler Engineer

Jan 2015Sep 2021 · 6 yrs 8 mos

Internship

Jun 2014Jan 2015 · 7 mos

Education

Yerevan State University

Bachelor's degree — radiophysics

Jan 2007Jan 2011

Yerevan State University

Master’s Degree

Jan 2013Jan 2015

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