Feb 2024 – Mar 2026 · 2 yrs 1 mo · Hyderabad · Hybrid

• Own end to end post silicon enablement of SLM IP for customer SoCs on ATE platforms
• Collaborate with DFT, Design, Analytics, R&D, and Test chip teams to define test strategies
• Enable SLM use cases including: Aging & reliability modeling;Vmin estimation and silicon margin analysis;Data driven post silicon optimization
• Lead customer engagements for test conditions definition, methodology alignment, and issue resolution
• Drive test Chip bring up and silicon data collection for analytics driven insights

Mar 2023 – Feb 2024 · 11 mos · Hyderabad · Hybrid

• Own end to end post silicon enablement of SLM IP for customer SoCs on ATE platforms
• Collaborate with DFT, Design, Analytics, R&D, and Test chip teams to define test strategies
• Enable SLM use cases including:
• Aging & reliability modeling
• Vmin estimation and silicon margin analysis
• Data driven post silicon optimization
• Lead customer engagements for test conditions definition, methodology alignment, and issue resolution

Dec 2019 – Feb 2023 · 3 yrs 2 mos · Hyderabad · Hybrid

• Executed playback simulations, vector conversions, and ATE compatibility checks, identifying internal force issues and ensuring smooth silicon bring up.
• Led ATE load board design reviews, resolving documentation and implementation gaps to ensure production ready test hardware.
• Owned Sort & Class Test Programs, including BSDL bring up, leakage, and VIX/VOX parametric enablement, supporting HVM, HTOL, and reliability testing.
• Drove yield improvement, test time reduction, and sustaining activities through close collaboration with fabs and OSATs (SPIL, KYEC, Ma Tek).
• Mentored new engineers, defined execution milestones, and ensured on time delivery across aggressive product schedules.
• Worked on BSDL bring up and enablement of Leakage Test and VIX/VOX parametric. enablement for Production.

Feb 2019 – Nov 2019 · 9 mos · Hyderabad, Telangana, India

• Collaborated with DFT and DV teams during pre silicon validation, providing testability feedback that enabled test time and vector memory reduction.
• Acted as a technical bridge between Design teams and 3rd party test teams, resolving ATE related issues efficiently.
• Performed standard cell characterization validation and authored silicon characterization reports based on silicon data analysis.

Jun 2018 – Feb 2019 · 8 mos · On-site

• Direct contribution to high volume Qualcomm MSM production with stable yield.
• Worked as Digital Lead for all digital blocks, providing technical leadership and successfully leading a team of Six members.
• Led pre silicon characterization planning and cross functional reviews with Design teams, ensuring first pass silicon readiness before wafer fab out.

Apr 2016 – Jun 2018 · 2 yrs 2 mos · On-site

• Test Engineer Consultant – Qualcomm Technologies
• End to end ownership of SCAN / MBIST / JTAG bring ups across multiple Snapdragon MSM nodes from first silicon to HVM.
• Worked Closely with DFT/DV Teams for the smooth Silicon bring ups
• Test Program development on new SOC products using Verigy Pin scale / Agilent 93K
• Supported wafer sort, final test, qualification, and production ramp
• Performed yield analysis, system to ATE correlation, and RMA support
• Reviewed and validated load board designs
• Released production test programs to offshore manufacturing sites (Multiple Fabs and OSATs)
• Supporting offshore foundry and test houses to ensure a low yield loss.

Nov 2012 – Apr 2016 · 3 yrs 5 mos · On-site

• Test Engineer Consultant – Qualcomm Technologies
• Led pre-fab characterization planning and reviews with design teams to ensure complete test coverage
• Executed rapid DC test bring up (Leakage, Pull up/Pull down, VOL/VOH, VIL/VIH) supporting product qualification timelines.
• Performed multi fab silicon characterization and generated correlation reports to analyze process variations
• Developed and delivered silicon characterization and production test programs from bring up through qualification.
• Generated silicon characterization reports, comparing measured results against design specifications.
• Implemented multisite DC characterization (X8, X12) using load board MUXing to improve test throughput.
• Executed low speed I/O timing characterization (setup, hold, margin analysis) across PVT corners, delivering validated limits for datasheet sign off.