Vishnu Kumar

Software Engineer

Noida, Uttar Pradesh, India23 yrs 3 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 16 years of experience in EDA software development.
  • Expert in Static Timing Analysis and SPICE flows.
  • Two patents awarded and one patent pending.
Stackforce AI infers this person is a highly skilled EDA software architect with extensive experience in semiconductor design tools.

Contact

Skills

Core Skills

Spice FlowsStatic Timing Analysis

Other Skills

Delay CalculationSignal IntegrityDistributed STAClock Mesh AnalysisBack AnnotationCycle-to-Cycle Jitter AnalysisIR aware timing AnalysisGlitch AnalysisC++CMultithreadingProblem SolvingTCLScriptingDebugging

About

Architect, Design and Implement EDA Software Solutions for Semiconductor Chip Designing tools for Static Timing Analysis(STA), Distributed-STA, Delay Calculation and Signal Integrity. 16 years of Software Product Development experience in C/C++ & Linux, defining software system implementation strategies and developing software for solving complex problems. Ample hands-on experience in developing new and enhancing existing applications in the field of EDA domain. Conversant with ASIC flows, at a flow and point tool level. Developed multiple SPICE based flows from conceptualization till the product level, for delay (base and SI) analysis, clock tree analysis and back annotation, signal EM, cycle-to-cycle Jitter analysis, IR aware timing and glitch analysis. They are in use for correlation, what if analysis and closing last few outliers. Experience in leading technical team for developing new and enhancing existing software applications to achieve business goal. Having two patents awarded and one patent pending and two publications Specialties: DC (Delay Calculation) SI Delay & Glitch SPICE flows Static Timing Analysis (STA) and D-STA (Distributed STA) Noise Characterizer Tools EDA Design Flows Software Architecture and Design IT Consulting, Designing, Debugging, and Automation Data Structure and Algorithms Multi-core and Multi-threaded Programming TCL Scripting C, C++, Unix, and Linux GDB, DBX, Valgrind, and Collector tools Team Management Problem solving

Experience

23 yrs 3 mos
Total Experience
7 yrs 9 mos
Average Tenure
19 yrs 2 mos
Current Experience

Cadence design systems

4 roles

Software Architect

Promoted

Oct 2020Present · 5 yrs 8 mos

Sr. Principal Software Eng (R&D)

Jul 2015Sep 2020 · 5 yrs 2 mos

  • Developing and enhancing SPICE based flows for correlation, what if analysis and closing last few outliers for delay (base and SI), clock mesh analysis and back annotation, flow for signal EM, and flow for cycle-to-cycle Jitter analysis, IR aware timing Analysis flow and glitch analysis and and recently started working on D-STA, IR aware STA and cycle-to-cycle Jitter analysis.
SPICE flowsDelay CalculationSignal IntegrityStatic Timing AnalysisDistributed STAClock Mesh Analysis+4

Principal Software Engineer

Promoted

Jul 2011Jun 2015 · 3 yrs 11 mos

Senior Member Of Technical Staff

Jan 2007Jun 2011 · 4 yrs 5 mos

Solidcore systems

Sr Software Engineer

Apr 2005Jan 2007 · 1 yr 9 mos

  • Worked on Server(System Controller), is responsible for monitoring and managing the Solidcore Security and Solidcore Change Control (clients)

Honeywell

Sr Software Engineer

Dec 2002Apr 2005 · 2 yrs 4 mos

  • software development in automation control system for batch processing industry

Education

Birla Institute of Technology and Science, Pilani

ME — Software Systems

Jan 2000Jan 2002

Malaviya National Institute of Technology Jaipur

BE — Electrical

Jan 1996Jan 2000

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