Jan 2023 – Aug 2023 · 7 mos · Ottawa, Ontario, Canada

• Employed DPI files to establish a connected comparison between RTL design and C models. Leveraged UVM methodology to perform comprehensive verification tasks.
• Worked with various modules including gearboxes with clock domain crossing, bus reorganization, and frame manipulation. Developed a strong understanding of these modules’ functionalities and verification requirements.
• Successfully executed gearbox verification tasks without c model using PRBS checker. Demonstrated proficiency in ensuring the integrity and reliability of gearboxes.
• Utilized Synopsys DVE and Verdi tools for verification and coverage. Worked with Linux systems for running simulations and compiling code, used P4 and Bit Bucket to access and update design files.
• Acquired hands-on experience with Catapult high-level synthesis tool and completed tutorials and practical labs, demonstrating a solid grasp of high-level synthesis concepts.
• Implemented automated scripts using Python to streamline repetitive tasks and displayed register tables in HTML with hyperlinks.

May 2022 – Aug 2022 · 3 mos · Edmonton, Alberta, Canada

• Built a FPGA accelerator and various prototyping projects while assisted with machine learning acceleration and stochastic computation research.
• Developed a convolutional neural network in Python for image classification, as foundation for future acceleration.
• Exposed to ASIC design flow, gained solid knowledge of design, synthesis and verification process.
• Developed strong academic writing skills, wrote a detailed research report on all design projects done in the lab.