Luat Vo

Product Engineer

Vietnam4 yrs 9 mos experience

Most Likely To Switch

Key Highlights

Expert in Memory Compiler Development and Custom IPs Design.
Strong background in RF/Microwave Engineering and 5G technologies.
Proficient in advanced simulation techniques and performance optimization.

Stackforce AI infers this person is a Semiconductor Engineer with expertise in Circuit Design and RF/Microwave Engineering.

Contact

Skills

Core Skills

Memory Compiler DevelopmentCustom Ips DesignRf/microwave Engineering

Other Skills

N3P HDP2PRF instancesN3E Multi Port Bit-cell AnalysisSS14 LPU UHSDP CompilerTSMC 12FFC Plus ULL HD2PRF CompilerN4P UHDSP CompilerSS4 RA1UHS CompilerOptimizing timing performance5G deployment researchMassive MIMOBeamformingDoherty Power AmplifiersADS toolKeysight ADSANSYS HFSSAntenna Design

About

Experienced Circuit Design Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Electronics, Memory Compiler Development, Custom IPs Design, RF/Microwave Engineering and Communications Network. Strong engineering professional with a Bachelor of Engineering (B.E.) focused on Electrical and Electronics Engineering from Programme de Formation d'Ingénieurs d' Excellence au Vietnam (PFIEV) of Ho Chi Minh City University of Technology. I am always eager to explore new challenges to keep me motivated every day.

Experience

4 yrs 9 mos

Total Experience

2 yrs 4 mos

Average Tenure

2 yrs 7 mos

Current Experience

Accuchip technology co., ltd

Senior Design Engineer

Nov 2023 – Present · 2 yrs 7 mos · Ho Chi Minh City, Vietnam

Synopsys inc

R&D Engineer

Sep 2021 – Nov 2023 · 2 yrs 2 mos · Ho Chi Minh City, Vietnam

N3P HDP2PRF instances (TSMC N3P Pseudo Two Port High Density Leakage Control Register File): Optimizing timing performance, perform race margin check, instance-level Monte Carlo simulation.
N3E Multi Port Bit-cell Analysis.
SS14 LPU UHSDP Compiler (Samsung 14nm LPU High Speed Dual Port SRAM): Porting Race Margin setup from eSilicon flow to Synopsys flow.
TSMC 12FFC Plus ULL HD2PRF Compiler (TSMC 12nm Two Port High Density Leakage Control Register File): Role involves performing Race Margin check, Instance-level Monte Carlo Simulation, Timing/Power/Leakage Full RC Simulations.
N4P UHDSP Compiler (TSMC 4nm Single Port Ultra High Density Leakage Control SRAM): Perform Instance-level Monte Carlo Simulation.
SS4 RA1UHS Compiler (Samsung 4nm LPP Ultra High Speed Single Port SRAM): Working as a design engineer. Perform Race Margin check, Instance-level Monte Carlo Simulation.

N3P HDP2PRF instancesN3E Multi Port Bit-cell AnalysisSS14 LPU UHSDP CompilerTSMC 12FFC Plus ULL HD2PRF CompilerN4P UHDSP CompilerSS4 RA1UHS Compiler+2

Viettel network corporation-branch of viettel group (vtnet)

Radio Frequency Optimization Engineer

Apr 2021 – May 2021 · 1 mo · Ho Chi Minh City, Vietnam · On-site

Research on 5G deployment options, and key technologies: Flexible slots, Scalable numerology, Massive MIMO, Beamfoeming.
Compare the 5G Core with the Evolved Packet Core (EPC) from LTE.

5G deployment researchMassive MIMOBeamformingRF/Microwave Engineering