Rajesh Barman

Product Engineer

Bengaluru, Karnataka, India2 yrs 6 mos experience

Key Highlights

  • Expert in Design and Verification Engineering.
  • Proficient in SystemVerilog and UVM methodologies.
  • Hands-on experience in 5G and semiconductor projects.
Stackforce AI infers this person is a Semiconductor and Telecommunications expert with a focus on Design and Verification Engineering.

Contact

Skills

Core Skills

Design Verification TestingFunctional Verification

Other Skills

SVUniversal Verification Methodology (UVM)XceliumSimVisionVmanagerIMCJenkinsUVMFunctional CoverageEthernetClearCaseVCSVerdiEtherNet/IPCase Tools

About

From an early age, I was fascinated by the intricate workings of technology and the power of innovation. This passion led me to pursue a career as a Design and Verification Engineer, where I could transform my love for problem-solving into tangible solutions. As a lifelong learner, I stay abreast of the latest developments in design and verification engineering, continuously expanding my knowledge and expertise. I am excited to be part of a field that pushes boundaries and shapes the future of technology. Here is a sneak peak of what i know: • Verilog • System Verilog • Universal Verification Methodology(UVM) • RTL Coding • Functional Coverage Hands on experience • Router 1X3 design and verification . SPI controller verification Behavioral skills • Communication skills • Collaborative • Organised

Experience

2 yrs 6 mos
Total Experience
1 yr 11 mos
Average Tenure
1 yr 5 mos
Current Experience

Cadence

Corp consultant(Design and Verification Engineer)

Jan 2025Present · 1 yr 5 mos · Bengaluru, Karnataka, India · On-site

  • Project: UCIe Controller IP Verification | Tools: Xcelium, SimVision, Vmanager, IMC, Jenkins
  • Studied RTL architecture & streaming top-level verification specification for UCIe controller IP
  • Developed ECC test cases (correctable & uncorrectable errors) for AXI_AR/R/B/W/AW RAMs across multiple IP configurations
  • Owned functional coverage closure and V-Plan updates: mainband coverage, register functional coverage with backdoor sample method, gearbox functional coverage, and IRQ functional coverage
  • Testbench updates and V-Plan updates aligned with RTL changes and specification revisions
  • Drove code coverage (CC) closure for ctrl_ip_top at 1024 & 512 data width for both single-stack and multi-stack configurations
  • Automated full CC refine flow: ported refines to cmd files, feature/module-wise segregation, back annotation, RTL auto-update scripts, and pipelined shell execution
  • Developed Python warning notifier with graph & mail reporting integrated with Jenkins CI pipeline
  • Implemented IRQ verification and IRQ functional coverage
  • Implemented telemetry counter verification
SVUniversal Verification Methodology (UVM)XceliumSimVisionVmanagerIMC+3

Aionsi

Design and Verification Engineer

Dec 2023Present · 2 yrs 6 mos · Bengaluru, Karnataka, India · On-site

  • Project: 5G Carrier Control IP Verification | Client: Ericsson | Tools: VCS, Verdi (Aug – Dec 2024)
  • Analysed 5G carrier control IP specification and authored detailed verification plan from design spec
  • Developed complete SV/UVM testbench from scratch — environment, agents, monitors, scoreboards for datapath checking
  • Developed SystemVerilog Assertions (SVA) for XCONs and MUX control paths
EthernetClearCaseVCSVerdiDesign Verification TestingFunctional Verification

Education

Central Institute of Technology, Kokrajhar

Bachelor of Technology

Jul 2017Oct 2021

Sankardev Academy,Nalbari

HS under AHSEC — Science Stream

Jan 2014Jan 2016

Sankardev Vidya Niketan,Nalbari

HSLC under SEBA — Schooling

Jan 2002Jan 2014

SANKARDEV ACADEMY, NALBARI

High School Diploma — AHSEC

Sharda Vidya Niketan

High School Diploma — SEBA

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