Aug 2024 – Present · 1 yr 10 mos · On-site

Aug 2024 – May 2026 · 1 yr 9 mos · On-site

• Designed and integrated RTL designs for Baker Hughes’s products. Developed test benches to validate the functionality of FPGA designs for Baker Hughes’s products which includes the simulation of the design. Conducted research into emerging FPGA technologies related to FPGA design techniques and toolsets. Analyzed and debugged existing FPGA designs, including HDL codes, simulation results and timing constraints. Performed synthesis and implementation for place and route operations on XILINX FPGAs using XILINX ISE Design Suite. Developed algorithms to improve the performance of existing FPGA designs in Baker Hughes products. Worked with hardware to define system requirements and performance which required the rebooting of hardware and testing the functionality of the RTL. Optimized existing RTL code to meet the timing constraints along with resource utilization while maintaining functionality of the design. Memory management for the Baker Hughes’s products which includes the organization of memory unit of CPU and FPGA, memory hierarchies and data transfer from CPU to FPGA and vice versa. Created detailed technical documentation for all design activities, including block diagrams, schematics, state machines, logic equations and register maps.

Jul 2022 – Aug 2024 · 2 yrs 1 mo · Bengaluru, Karnataka, India

Jul 2022 – Aug 2024 · 2 yrs 1 mo · Bengaluru, Karnataka, India

• Design and validation of testcases along with feature deployment for Customer FPGA Prototyping team working on HAPS prototyping platform. Performing OSTs for Synopsys tools Protocompiler and VCS newer versions for GPUs and SoC design of NVIDIA. It includes ucdb generation from RTL, partitioning the design, mapping the design in individual FPGAs and using XILINX Vivado to generate bitfiles and hardware testing. Collaboration with the RnD team to integrate,validate and deploy new feature for Synopsys tools Protocompiler and Synplify for Customer, enabling smooth prototyping and debugging of GPUs and SoCs. Gained hands-on experience in loading/booting Linux/Embedded Linux on Virtual Platforms in a Linux environment. Resolving PNR congestion issues to generate bitfile using XILINX Vivado using multiple vivado strategies. Using Xilinx Vivado to solve the customer issues regarding pnr. Management of memory in the HAPS for NVIDIA’s GPU and SoCs which included the understanding the memory orientation in the design and its equivalent implementation on HAPS with RISC V processors. Resolve and support Gateway for NVIDIA. Gateway is a tool which is used to connect the hardware system from a far site and test the bitfiles on it. Developed communication skills by drafting professional functional specifications and design documents, ensuring clarity and alignment among team members.

Jun 2020 – Dec 2020 · 6 mos

• Designed Verilog based Traffic light controller. Designed Verilog based MAC unit. Designed Verilog based ALU.