Maksim Ananev

Software Engineer

Portugal10 yrs 11 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in high-performance FPGA and RTL systems
  • Strong background in low-latency datapath design
  • Hands-on experience in aerospace and radar domains
Stackforce AI infers this person is a highly skilled FPGA and ASIC engineer with expertise in aerospace and real-time systems.

Contact

Skills

Core Skills

Asic DesignEmbedded SystemsFpga DesignVideo ProcessingDsp

Other Skills

C (Programming Language)Встроенное ПОTCLDigital Signal ProcessingVerilogSysVerilogVHDLFPGAEmbedded SoftwareSystemVerilogXilinx VivadoQtPythonModelsimQuartus

About

Digital Design Engineer specializing in high-performance FPGA and RTL systems for real-time applications. Strong background in low-latency datapath design, high-speed interfaces, and timing-critical systems, with experience spanning aerospace, radar, and compute acceleration domains. Hands-on expertise in: • SystemVerilog/VHDL RTL development • High-throughput pipelines and hardware acceleration • FPGA system integration and debugging • ASIC-oriented development: RTL for high-speed interfaces IP, validation, lint/CDC flows Focused on delivering deterministic, high-performance hardware systems. Currently open to remote or project opportunities

Experience

10 yrs 11 mos
Total Experience
2 yrs 8 mos
Average Tenure
3 yrs 1 mo
Current Experience

Synopsys inc

ASIC Digital Design Staff Engineer

May 2023Present · 3 yrs 1 mo · Агломерация Порту · On-site

C (Programming Language)Встроенное ПОASIC DesignEmbedded Systems

Aviasystems

FPGA Engineer

Mar 2021Apr 2023 · 2 yrs 1 mo

  • Development of aircraft's MFD. Video stream and interfaces(DisplayPort, LVDS, HDMI, VGA, SDI), PCI-e , DDR, GX transceiver. Aviation protocols ARINC429,708, MIL-STD-1553 e.t.c.
  • RTL in the SysVerilog (and C++ for the software processors);
  • Scripts in Python and TCL.
C (Programming Language)TCLFPGA DesignVideo Processing

Zaslon

FPGA Engineer

Oct 2018Mar 2021 · 2 yrs 5 mos

  • Development of DSP for radar systems
  • RTL in Verilog/SysVerilog language;
  • Writing workplace's software for interacting with device (Using the QT
  • framework, C++)
TCLDigital Signal ProcessingFPGA DesignDSP

Electroavtomatica

FPGA Engineer

Jun 2015Oct 2018 · 3 yrs 4 mos

  • RTL in VHDL language;
  • Warranty support of device including long-term foreign business trips (Algeria, Myanmar).
VHDLFPGA Design

Education

Saint Petersburg State University of Aerospace and Instrumentation

Master's degree — Технологии радиолокационных систем

Sep 2011Jul 2017

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