Wootak Ryu — Software Engineer

As an engineer with extensive experience in 5nm and 4nm SoC development, I have performed timing, power, and signal integrity analysis using industry-standard EDA tools such as Design Compiler (DC), PrimeTime, Formality, VCLP, and SpyGlass. I have conducted signal, equivalence, and timing analysis across a wide range of IP blocks, including USB 1.0/2.0, PCIe 4.0, Custom IP, and LPDDR5. My expertise also includes SI/PI integrity verification, PPA optimization, and low-power architecture analysis using UPF for multi-voltage designs. As a Synopsys Prime Series (PrimeTime / PrimeShield) PAE, I supported global customers(Samsung/ARM/QCOM/Google/ETC) by diagnosing complex timing and reliability issues, optimizing analysis environments, and ensuring spice-accurate results. With end-to-end experience across design, verification, and analysis, I am capable of supporting high-quality ASIC development. Tools: Experienced with 3D-IC, PrimeClock (jitter), HS/HG, VSA, SMVA, PT2SPICE and various Prime* advanced analysis features for timing, reliability, and variability signoff. Hands-on experience with DC/DCG/DC-NXT, Formality, VCLP, SpyGlass, ICC2, and Fusion Compiler (FC) across synthesis, equivalence checking, and physical/constraint verification flows. Scripting: Proficient in TCL, sed, csh, bash, and awk, with extensive experience in flow automation, data-driven debugging, and large-scale report processing.

Stackforce AI infers this person is a Semiconductor Engineering expert specializing in SoC development and analysis.

Location: Hwaseong, Gyeonggi, South Korea

Experience: 5 yrs 5 mos