Rajagopal S Prabhu — Software Engineer

I am a Digital Design Engineer specializing in PCIe IP subsystems, RTL development, and high-speed digital architectures. My work spans PCIe controller/PHY integration, PIPE-based data paths, clock-domain crossing (CDC/RDC), reset strategies, and building robust subsystem-level RTL. I bring a solid understanding of PCIe fundamentals along with growing experience in multi-protocol PHY environments and complex SoC integration. I have hands-on exposure to functional safety (ISO 26262), including multiple safety work products, requirement decomposition and integrating safety mechanisms into hardware designs. I also work extensively with SpyGlass for lint, CDC, and RDC analysis, ensuring design quality and structural correctness. Alongside my RTL responsibilities, I have decent debugging skills and awareness of verification methodologies, which help me collaborate effectively with DV teams. I am passionate about continuous learning and solving deep design challenges—whether it’s understanding tricky CDC behaviors, improving RTL readability, debugging simulation failures or analyzing high-speed protocol flows. I enjoy contributing to reliable, maintainable digital systems and am always looking for opportunities that push me technically and help me grow as a well-rounded RTL and SoC design engineer.

Stackforce AI infers this person is a Digital Design Engineer specializing in high-speed digital architectures and functional safety.

Location: Bengaluru, Karnataka, India

Experience: 2 yrs 11 mos