Kotturi Sai Harshitha — Software Engineer

Highly self-motivated Sr RTL Design Engineer with 3 years of specialized experience in ASIC IP Digital Design, focusing on High-Speed SerDes PHY (32G/128G) at Synopsys. Passionate about pushing the boundaries of high-speed interface design while ensuring design quality and performance excellence. 🔧 Core Expertise: • RTL Design & Micro-architecture for High-Speed SerDes PHY (32G/128G) • Design Quality Sign-off: LINT, CDC, RDC closure using SpyGlass/VC SpyGlass • Firmware Development for PHY calibrations, adaptations & training algorithms • PCIe5 Area Optimization & Power Analysis • Post-Silicon Debug • Cross-functional Collaboration with Analog, Verification & Customer teams 💡 Key Achievements: ✓ Led LINT, CDC, and RDC closure for multiple SerDes IPs using hierarchical SpyGlass flows ✓ Engineered PCIe5 area-efficient designs through FSM optimization and power-timing trade-off analysis ✓ Developed scalable, backward-compatible scripts for design quality checks across SerDes X3 integration ✓ Resolved critical post-silicon bring-up issues through firmware fixes ✓ Mentored junior engineers on RTL design practices and debugging methodologies 🛠️ Technical Arsenal: RTL Design (Verilog), High-Speed SerDes PHY, PCIe, Ethernet, SpyGlass/VC SpyGlass, VCS, Verdi, DVE, Python, TCL, Makefile, Perforce, Cursor AI IDE

Stackforce AI infers this person is a High-Speed Digital Design Engineer with expertise in ASIC and firmware development.

Location: Andhra Pradesh, India

Experience: 3 yrs