Santhosh Ravisankar — Software Engineer
Analog Layout Design Engineer --> Tech Node : 2nm , 3 nm , 5nm , 7nm , 16nm , 180nm --> GAAFET , FINFET , CMOS --> Projects : DDR5/LPDDR5 , PLL --> Tools : Cadence Virtuoso , Calibre , ICV , Totem --> LVS , DRC and other types of check required for quality and integration --> Skilled in RV, Matching, EM & IR, Antenna and density optimization
Stackforce AI infers this person is a skilled Analog Layout Design Engineer with expertise in semiconductor and automotive industries.
Location: Bengaluru, Karnataka, India
Experience: 5 yrs 9 mos
Skills
- Analog Layout Design
- Reliability Verification
Career Highlights
- Expert in Analog Layout Design across multiple tech nodes.
- Proficient in Cadence tools for layout verification.
- Innovated technology for solar-powered electric vehicles.
Work Experience
Tessolve
Layout Design Engineer - 2 (1 yr 8 mos)
HCL Technologies
Analog Layout Engineer (3 yrs 1 mo)
Airports Authority of India
Summer Intern (0 mo)
SOLARIS
ELECTRICAL CORE MEMBER (1 yr)
BHAVINI PFBR Atomic Power Station
In-Plant Training (0 mo)
Chennai Metro Rail Limited
In-Plant Training (0 mo)
Education
Bachelor's degree at Sri Sairam Engineering College