Chris Papademetrious

CTO

Allentown, Pennsylvania, United States27 yrs experience

Highly Stable

Key Highlights

Stackforce AI infers this person is a Semiconductor Applications Engineer with extensive experience in EDA tools.

EdaAsicTechnical WritingTclDftApplications EngineeringStaSynthesisTiming Closure

VerilogSoCIntegrated Circuit DesignVLSIICFPGARTL designStatic Timing AnalysisPerlDebuggingSemiconductorsVHDLPhysical DesignSDC constraintsOxygen

27 yrs

Total Experience

27 yrs

Average Tenure

27 yrs

Current Experience

5 roles

Promoted

Aug 2023 – Present · 2 yrs 10 mos · Allentown, Pennsylvania, United States · Remote

EDATCLASICVerilogSoCIntegrated Circuit Design+11

Jun 2018 – Jul 2023 · 5 yrs 1 mo · Allentown, Pennsylvania, United States · Remote

Technical writer (and pseudo-PAE) for PrimeTime, Synopsys Tcl shell, SDC constraints
Developed, supported, and maintained Oxygen/DITA/Git authoring/production environment
Developed FrameMaker-to-DITA conversion flow - variables, conditional text, bitmap/vector graphics, equations, metadata...
Implemented Git release branch methodology with automatic merge-forward, conflict resolution detection
DITA Open Toolkit - contributor and technical committee member

TCLSDC constraintsOxygenDITAGitFrameMaker+2

Nov 2010 – Jun 2018 · 7 yrs 7 mos · Allentown, Pennsylvania, United States · Remote

Technical writer (and pseduo-PAE) for DFT Compiler, BSD Compiler, LogicBIST, HDL Compiler, Liberty NCX
Helped roll out Liberty NCX, DFT physically aware test point insertion, LogicBIST, DFTMAX Ultra, IEEE 1500 core wrapping
Wrote many SolvNet articles and application notes (and won "most-used SolvNet article" award multiple times)
Continued in PAE-like role for all products - R&D project reviews, functionality/algorithm discussions, preproduction feature testing, bug filing

DFT CompilerBSD CompilerLogicBISTHDL CompilerLiberty NCXTechnical Writing+1

Promoted

Nov 2003 – Dec 2011 · 8 yrs 1 mo · Allentown, Pennsylvania, United States · Remote

Lead rollout engineer for multi-scenario analysis (DMSA), ECO estimation, physically exclusive clocks, PLL jitter/drift, HyperScale features - collaborated with R&D on functionality, algorithms, UI
Developed, deployed, and supported original Tcl-based exhaustive path-based analysis, DMSA/ECO hold-fixing, PrimeTime/HSPICE correlation features
Lead rollout engineer for PrimeTime VX statistical STA tool, developed latin hypercube sampling engine and Monte Carlo HSPICE correlation system (with adaptive sweeping)
Wrote many detailed "whitepaper" articles (clock gating, exhaustive PBA, UITE-461, CRPR) that continue to be among the most popular articles on SolvNetPlus

TclDMSAECO estimationPLL jitterPrimeTimeHSPICE+2

Oct 1997 – Apr 2002 · 4 yrs 6 mos · Allentown, Pennsylvania, United States · Hybrid

Delivered pre-sales and post-sales support for synthesis, signoff, DFT, formal equivalence tools
Served as regional specialist in pipelined datapath, behavioral RTL synthesis, RTL-to-gates formal equivalence

SynthesisSignoffDFTFormal EquivalenceApplications Engineering

Apr 2002 – Nov 2003 · 1 yr 7 mos · Chester Springs, Pennsylvania, United States · Hybrid

Performed all synthesis, timing closure, signoff, ATPG tasks for a gigabit Ethernet offload processor chip (using a proprietary behavioral-to-synthesizable Verilog compiler)
Developed automated incremental (make-based) synthesis system based on RTL in revision control
Debugged simulation issues in in-house RTL, PCI-X RTL IP

SynthesisTiming ClosureATPGVerilog